ep2a40b724i8 Altera Corporation, ep2a40b724i8 Datasheet - Page 24

• Manufacturer Part Number: ep2a40b724i8
• Description: Programmable Logic Device Family
• Manufacturer: Altera Corporation

APEX II Programmable Logic Device Family Data Sheet
24
Row I/O pin
Column I/O
pin
LE
ESB
Local
interconnect
MegaLAB
interconnect
Row
FastTrack
interconnect
Column
FastTrack
interconnect
FastRow
interconnect
Table 5. APEX II Routing Scheme
Source
I/O Pin
Row
v
Column
I/O Pin
v
Table 5
other.
Product-Term Logic
The product-term portion of the MultiCore architecture is implemented
with the ESB. The ESB can be configured to act as a block of macrocells on
an ESB-by-ESB basis. 32 inputs from the adjacent local interconnect feed
each ESB; therefore, the either MegaLAB or the adjacent LAB can drive the
ESB. Also, nine ESB macrocells feed back into the ESB through the local
interconnect for higher performance. Dedicated clock pins, global signals,
and additional inputs from the local interconnect drive the ESB control
signals.
In product-term mode, each ESB contains 16 macrocells. Each macrocell
consists of two product terms and a programmable register.
shows the ESB in product-term mode.
v
LE
summarizes how elements of the APEX II architecture drive each
ESB
v
Interconnect
Local
v
v
v
v
v
Destination
Interconnect
MegaLAB
v
v
v
v
v
Interconnect
FastTrack
Row
v
v
v
v
Interconnect
FastTrack
Column
v
v
v
v
v
Altera Corporation
Figure 13
Interconnect
FastRow
v