ep2a40b724i8 Altera Corporation, ep2a40b724i8 Datasheet - Page 46

• Manufacturer Part Number: ep2a40b724i8
• Description: Programmable Logic Device Family
• Manufacturer: Altera Corporation

APEX II Programmable Logic Device Family Data Sheet
Figure 30. APEX II IOE in DDR Output I/O Configuration
46
Column, Row
Interconnect
or Local
12 Peripheral
Signals
Dedicated
Clocks
Eight
Chip-Wide Reset
Register Delay
The APEX II IOE operates in bidirectional DDR mode by combining the
DDR input and DDR output configurations.
APEX II I/O pins transfer data on a DDR bidirectional bus to support
DDR SDRAM at 167 MHz (334 Mbps). The negative-edge-clocked OE
register is used to hold the OE signal inactive until the falling edge of the
clock. This is done to meet DDR SDRAM timing requirements. QDR
SRAMs are also supported with DDR I/O pins on separate read and write
ports.
Logic Array
to Output
Register Delay
Logic Array
to Output
Enable Delay
Output Clock
Output Register
Output Register
OE Register
OE Register
ENA
CLRN/PRN
CLRN/PRN
CLRN/PRN
CLRN/PRN
D
ENA
D
ENA
D
ENA
D
Q
Q
Q
Q
Used for
DDR SDRAM
clk
Drive Strength Control
Open-Drain Output
Slew Control
Propagation
t
Output
ZX
Delay
Output
Delay
OE Register
t
CO
Delay
VCCIO
Altera Corporation
VCCIO
Optional
PCI Clamp
Bus-Hold
Circuit
Programmable
Pull-Up