ep2a40b724i8 Altera Corporation, ep2a40b724i8 Datasheet - Page 12

• Manufacturer Part Number: ep2a40b724i8
• Description: Programmable Logic Device Family
• Manufacturer: Altera Corporation

APEX II Programmable Logic Device Family Data Sheet
Figure 5. APEX II Logic Element
12
labclkena1
labclkena2
Chip-Wide
labclk1
labclk2
labclr1
labclr2
Reset
data1
data2
data3
data4
Look-Up
Asynchronous
Clear/Preset/
(LUT)
Table
Load Logic
Clock &
Clock Enable
Select
Carry-Out
Carry-In
Chain
Carry
Each LE’s programmable register can be configured for D, T, JK, or SR
operation. The register’s clock and clear control signals can be driven by
global signals, general-purpose I/O pins, or any internal logic. For
combinatorial functions, the register is bypassed and the output of the
LUT drives the outputs of the LE.
Cascade-In
Cascade
Chain
Cascade-Out
Synchronous
LAB-wide
Load
Synchronous
Load & Clear
Logic
Synchronous
LAB-wide
Clear
D
ENA
CLRN
PRN
Register Bypass
Packed
Register Select
Q
Register
Programmable
To F astTrack Interconnect,
MegaLAB Interconnect,
or Local Interconnect
To F astTrack Interconnect,
MegaLAB Interconnect,
or Local Interconnect
Altera Corporation