ep2a40b724i8 Altera Corporation, ep2a40b724i8 Datasheet - Page 51

• Manufacturer Part Number: ep2a40b724i8
• Description: Programmable Logic Device Family
• Manufacturer: Altera Corporation

Altera Corporation
Note to
(1)
Table 10. APEX II Supported I/O Standards
LVTTL
LVCMOS
2.5 V
1.8 V
1.5 V
3.3-V PCI
3.3-V PCI-X
LVDS
LVPECL
PCML
HyperTransport
Differential HSTL
GTL+
HSTL class I and II
SSTL-2 class I and II
SSTL-3 class I and II
AGP (1 and 2 )
CTT
Differential HSTL is only supported on the eight dedicated global clock pins and four dedicated high-speed PLL
clock pins.
Table
I/O Standard
10:
f
(1)
Table 10
For more information on I/O standards supported by APEX II devices,
see
APEX II devices contain eight I/O banks, as shown in
blocks within the right I/O banks contain circuitry to support high-speed
True-LVDS, LVPECL, PCML, and HyperTransport inputs, and another
two blocks within the left I/O banks support high-speed True-LVDS,
LVPECL, PCML, and HyperTransport outputs. All other standards are
supported by all I/O banks.
Application Note 117 (Using Selectable I/O Standards in Altera
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
Differential
Differential
Differential
Differential
Differential
Voltage referenced
Voltage referenced
Voltage referenced
Voltage referenced
Voltage referenced
Voltage referenced
describes the I/O standards supported by APEX II devices.
Type
APEX II Programmable Logic Device Family Data Sheet
Voltage (V
Reference
Input
N/A
1.0
0.75
1.25
1.5
1.32
1.5
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
(V)
REF
)
(V
Voltage
Supply
Output
CCIO
N/A
3.3
3.3
2.5
1.8
1.5
3.3
3.3
3.3
3.3
3.3
2.5
1.5
1.5
2.5
3.3
3.3
3.3
) (V)
Figure
Termination
(V
Voltage
Board
31. Two
TT
N/A
1.5
0.75
1.25
1.5
1.5
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Devices).
) (V)
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