ep2a40b724i8 Altera Corporation, ep2a40b724i8 Datasheet - Page 53

• Manufacturer Part Number: ep2a40b724i8
• Description: Programmable Logic Device Family
• Manufacturer: Altera Corporation

Altera Corporation
Each bank can support multiple standards with the same V
and output pins. Each bank can support one voltage-referenced I/O
standard, but it can support multiple I/O standards with the same V
voltage level. For example, when V
LVTTL, LVCMOS, 3.3-V PCI, and SSTL-3 for inputs and outputs. When
the True-LVDS banks are not used for LVDS I/O pins, they support all of
the other I/O standards except HSTL Class II output.
True-LVDS Interface
APEX II devices contain dedicated circuitry for supporting differential
standards at speeds up to 1.0 Gbps. APEX II devices have dedicated
differential buffers and circuitry to support LVDS, LVPECL,
HyperTransport, and PCML I/O standards. Four dedicated high-speed
PLLs (separate from the general-purpose PLLs) multiply reference clocks
and drive high-speed differential serializer/deserializer channels. In
addition, CDS circuitry at each receiver channel corrects any fixed clock-
to-data skew. All APEX II devices support 36 input channels, 36 output
channels, two dedicated receiver PLLs, and two dedicated transmitter
PLLs.
The True-LVDS circuitry supports the following standards and
applications:
APEX II devices support source-synchronous interfacing with LVDS,
LVPECL,PCML, or HyperTransport signaling at up to 1 Gbps. Serial
channels are transmitted and received along with a low-speed clock. The
receiving device then multiplies the clock by a factor of 1, 2, or 4 to 10. The
serialization/deserialization rate can be any number from 1, 2, or 4 to 10
and does not have to equal the clock multiplication value.
For example, an 840-Mbps LVDS channel can be received along with an
84-MHz clock. The 84-MHz clock is multiplied by 10 to drive the serial
shift register, but the register can be clocked out in parallel at 8- or 10-bits
wide at 84 or 105 MHz. See
RapidIO
POS-PHY Level 4
Utopia IV
HyperTransport
APEX II Programmable Logic Device Family Data Sheet
Figures 32
CCIO
and 33.
is 3.3 V, a bank can support
CCIO
for input
CCIO
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