ep2a40b724i8 Altera Corporation, ep2a40b724i8 Datasheet - Page 58

• Manufacturer Part Number: ep2a40b724i8
• Description: Programmable Logic Device Family
• Manufacturer: Altera Corporation

APEX II Programmable Logic Device Family Data Sheet
MultiVolt I/O
Interface
58
Data Rate Maximum operating speed
TCCS
SW
Table 13. APEX II Flexible-LVDS Timing Specification
Symbol
Transmitter channel-to-channel
skew
Receiver sampling window
Timing Parameter Definition
Pre-programmed CDS may also be used to resolve clock-to-data skew
greater than 50% of the bit period. However, internal logic must be used
to implement the byte alignment circuitry for this operation.
Flexible-LVDS I/O Pins
A subset of pins in the top two I/O banks supports interfacing with
Flexible-LVDS, LVPECL, and HyperTransport inputs. These
Flexible-LVDS input pins include dedicated LVDS, LVPECL, and
HyperTransport input buffers. A subset of pins in the bottom two I/O
banks supports interfacing with Flexible-LVDS and HyperTransport
outputs. These Flexible-LVDS output pins include dedicated LVDS and
HyperTransport output buffers. The Flexible-LVDS pins do not require
any external components except for 100- termination resistors on
receiver channels. These pins do not contain dedicated
serialization/deserialization circuitry; therefore, internal logic is used to
perform serialization/deserialization functions.
The EP2A15 and EP2A25 devices support 56 input and 56 output
Flexible-LVDS channels. The EP2A40 and larger devices support 88 input
and 88 output Flexible-LVDS channels. All APEX II devices support the
Flexible-LVDS interface up to 400 Mbps (DDR) per channel. Flexible-
LVDS pins along with the True-LVDS pins provide up to 144-Gbps total
device bandwidth.
specification.
The APEX II architecture supports the MultiVolt I/O interface feature,
which allows APEX II devices in all packages to interface with systems of
different supply voltages. The devices have one set of V
internal operation and input buffers (VCCINT), and another set for I/O
output drivers (VCCIO).
1,100
Min
Table 13
-7
Max
400
700
shows the Flexible-LVDS timing
1,400
Speed Grade
Min
-8
Max
311
900
1,400
Min
Altera Corporation
-9
CC
Max
pins for
311
900
Mbps
Unit
ps
ps