ep2a40b724i8 Altera Corporation, ep2a40b724i8 Datasheet - Page 60

• Manufacturer Part Number: ep2a40b724i8
• Description: Programmable Logic Device Family
• Manufacturer: Altera Corporation

APEX II Programmable Logic Device Family Data Sheet
General-
Purpose PLLs
Figure 35. APEX II General-Purpose PLL
60
inclock
f
bin
n
Signals can be driven into APEX II devices before and during power-up
without damaging the device. In addition, APEX II devices do not drive
out during power-up. Once operating conditions are reached and the
device is configured, APEX II devices operate as specified by the user.
APEX II devices have ClockLock, ClockBoost, and ClockShift features,
which use four general-purpose PLLs (separate from the four dedicated
True-LVDS PLLs) to provide clock management and clock-frequency
synthesis. These PLLs allow designers to increase performance and
provide clock-frequency synthesis. The PLL reduces the clock delay
within a device. This reduction minimizes clock-to-output and setup
times while maintaining zero hold times. The PLLs, which provide
programmable multiplication, allow the designer to distribute a low-
speed clock and multiply that clock on-device. APEX II devices include a
high-speed clock tree: unlike ASICs, the user does not have to design and
optimize the clock tree. The PLLs work in conjunction with the APEX II
device’s high-speed clock to provide significant improvements in system
performance and bandwidth.
The PLLs in APEX II devices are enabled through the Quartus II software.
External devices are not required to use these features.
general-purpose PLL features for APEX II devices.
APEX II general-purpose PLL.
Number of PLLs
Table 15. APEX II General-Purpose PLL Features
4
Comparator
Phase
Note (1)
ClockBoost
m/(n
Voltage-Controlled
Feature
Phase Shift
Oscillator
Circuitry
k, v)
m
Number of External
Clock Outputs
k
v
8
Figure 35
Table 15
Altera Corporation
clock0
clock1
Feedback Inputs
Number of
shows an
shows the
2