ep2a40b724i8 Altera Corporation, ep2a40b724i8 Datasheet - Page 54

• Manufacturer Part Number: ep2a40b724i8
• Description: Programmable Logic Device Family
• Manufacturer: Altera Corporation

APEX II Programmable Logic Device Family Data Sheet
Figure 32. True-LVDS Receiver Diagram
Notes to
(1)
(2)
(3)
54
Two sets of 18 receiver channels are located in each APEX II device. Each set of 18 channels has one receiver PLL.
W = 1, 2, 4 to 10
J = 1, 2, 4 to 10
W does not have to equal J. When J = 1 or 2, the deserializer is bypassed. When J = 2, DDR I/O registers are used.
These clock pins drive receiver PLLs only. They do not drive directly to the logic array. However, the receiver PLL
can drive the logic array via a global clock line.
RX_CLK1 (3)
Figure
32:
Receiver
Channel
Receiver
Channel
Receiver
Channel
Receiver
PLL1
+
–
+
–
+
–
W
J
W
Notes
Receiver Channel 1
Receiver Channel 2
Receiver Channel 18
(1),
(2)
Deserializer
J Bits Wide
Altera Corporation
Data to
LEs
To Global
Clock