ep2a40b724i8 Altera Corporation, ep2a40b724i8 Datasheet - Page 55

• Manufacturer Part Number: ep2a40b724i8
• Description: Programmable Logic Device Family
• Manufacturer: Altera Corporation

Altera Corporation
Figure 33. True-LVDS Transmitter Diagram
Notes to
(1)
(2)
Global Clock
from Receiver
or System Clock
TXOUTCLOCK1
Transmitter
Channel
Transmitter
Channel
Two sets of 18 transmitter channels are located in each APEX II device. Each set of 18 channels has one transmitter
PLL.
W = 1, 2, 4 to 10
J = 1, 2, 4 to 10
W does not have to equal J. When J = 1 or 2, the deserializer is bypassed. When J = 2, DDR I/O registers are used.
Figure
33:
Transmitter
Channel
Transmitter
Clock-Data Synchronization
In addition to dedicated serial-to-parallel converters, APEX II True-LVDS
circuitry contains CDS circuitry in every receiver channel. The CDS
feature can be turned on or off independently for each receiver channel.
There are two modes for the CDS circuitry: single-bit mode, which
corrects a fixed clock-to-data skew of up to ±50% of the data bit period,
and multi-bit mode, which corrects any fixed clock-to-data skew.
PLL1
W
W
J
Notes
Transmitter Channel 1
Transmitter Channel 2
Transmitter Channel 18
APEX II Programmable Logic Device Family Data Sheet
(1),
(2)
Serializer
J Bits Wide
Data from
LEs
55