at85c51snd3 ATMEL Corporation, at85c51snd3 Datasheet - Page 104

• Manufacturer Part Number: at85c51snd3
• Description: At85c51snd3 Single-chip Digital Audio Decoder - Encoder With Usb 2.0 Interface
• Manufacturer: ATMEL Corporation

Suspend, Wake-Up and
Resume
Detach
104
AT85C51SND3B
•
•
•
•
ADDEN and UADD shall not be written at the same time.
UADD contains the default address 00h after a power-up or USB reset.
ADDEN is cleared by hardware:
•
•
•
When this bit is cleared, the default device address 00h is used.
After a period of 3 ms during which the USB line was inactive, the controller switches to
the full-speed mode and triggers (if enabled) the SUSPI (suspend) interrupt. The firm-
ware may then set the FRZCLK bit.
The CPU can also, depending on software architecture, enter in the idle mode to lower
again the power consumption.
There are two ways to recover from the “Suspend” mode:
•
•
There are no relationship between the SUSPI interrupt and the WAKEUPI interrupt: the
WAKEUPI interrupt is triggered as soon as there are non-idle patterns on the data lines.
Thus, the WAKEUPI interrupt can occurs even if the controller is not in the “suspend”
mode.
When the WAKEUPI interrupt is triggered, if the SUSPI interrupt bit was already set, it is
cleared by hardware.
When the SUSPI interrupt is triggered, if the WAKEUPI interrupt bit was already set, it is
cleared by hardware.
The reset value of the DETACH bit is 1.
It is possible to re-enumerate a device, simply by setting and clearing the DETACH bit.
•
the host sends a SETUP command (SET_ADDRESS(addr)),
the firmware records that address in UADD, but keep ADDEN cleared,
the USB device sends an IN command of 0 bytes (IN 0 Zero Length Packet),
then, the firmware can enable the USB device address by setting ADDEN. The only
accepted address by the controller is the one stored in UADD.
after a power-up reset,
when an USB reset is received,
or when the macro is disabled (USBE cleared)
First one is to clear the FRZCLK bit. This is possible if the CPU is not in the Idle
mode.
Second way, if the CPU is “idle”, is to enable the WAKEUPI interrupt (WAKEUPE
set). Then, as soon as an non-idle signal is seen by the controller, the WAKEUPI
interrupt is triggered. The firmware shall then clear the FRZCLK bit to restart the
transfer.
If the USB device controller is in full-speed mode, setting DETACH will disconnect
the pull-up on the D+ or D- pad (depending on full or low speed mode selected).
Then, clearing DETACH will connect the pull-up on the D+ or D- pad.
7632D–MP3–01/07