at85c51snd3 ATMEL Corporation, at85c51snd3 Datasheet - Page 29

• Manufacturer Part Number: at85c51snd3
• Description: At85c51snd3 Single-chip Digital Audio Decoder - Encoder With Usb 2.0 Interface
• Manufacturer: ATMEL Corporation

Clock Generator
480 MHz PLL
7632D–MP3–01/07
Figure 16. Crystal Connection
The clock generator provides the oscillator and higher frequency clocks to the System,
the DFC, the memory controllers: Nand Flash and MMC controllers, the USB and the
high speed Serial I/O port. It is based on a 480 MHz PLL namely the PLL clock followed
by a frequency divider giving a broad range of available clock frequency: the CLOCK
GEN clocks.
The clock generation is enabled by setting CKGENE bit in CKEN (see Table 32).
The PLL is enabled by setting PLLEN bit in CKEN and reports a filtered lock status by
the PLOCK Flag in CKEN.
As soon as the PLL is locked, the generated clocks can be used by the peripherals as
detailed in the following sections.
Figure 17. Clock Generator Block Diagram and Symbol
The PLL is based on a Phase Frequency Comparator and Lock Detector block (PFLD)
which makes the comparison between the reference clock coming from the 4-bit N
divider (PLLN3:0 + 1 in PLLCLK) and the reverse clock coming from either fixed fre-
quencies or the 4-bit R divider (PLLR3:0 + 1 in PLLCLK) and generates some pulses on
the Up or Down signal depending on the edge position of the reverse clock. These
pulses feed the Charge Pump block (CHP) that generates a voltage reference to the
480 MHz Voltage Controlled Oscillator (VCO) by injecting or extracting charges from an
internal filter. The reverse clock selection mechanism is implemented in order to support
many oscillator frequencies and to minimize the PLL output jitter.
CLOCK
OSC
CKGENE
CKEN.7
480 MHz PLL
PLLEN
CKEN.6
APVSS
Clock Generator Symbol
CLOCK
C1
C2
GEN
PLL Clock
PLOCK
CKEN.4
Q
X1
X2
Generator
Divider
Clock
OSC
120 MHz
60 MHz
48 MHz
40 MHz
30 MHz
24 MHz
20 MHz
16 MHz
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