at85c51snd3 ATMEL Corporation, at85c51snd3 Datasheet - Page 166
at85c51snd3
Manufacturer Part Number
at85c51snd3
Description
At85c51snd3 Single-chip Digital Audio Decoder - Encoder With Usb 2.0 Interface
Manufacturer
ATMEL Corporation
Datasheet
1.AT85C51SND3.pdf
(271 pages)
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AT85C51SND3B
Table 181. ACOLG Register (AT85C51SND3B1 and AT85C51SND3B2 only)
ACOLG (2.ECh) – Audio Codec Left Output Gain Register
Reset Value = 0000 0000b
Table 182. ACIPG Register
ACIPG (2.EDh) – Audio Codec Input Preamplifier Gain Register
Reset Value = 0000 0000b
Table 183. ADICON0 Register
ADICON0 (2.EEh) – Audio DAC Interface Control Register 0
Number
Number
Number
7-5
4-0
7-4
2-0
7-5
Bit
Bit
Bit
7
7
3
7
4
3
-
-
-
Mnemonic Description
Mnemonic Description
Mnemonic Description
AOLG4:0
AIPG4:0
CSPOL
AILPG
DSIZE
Bit
Bit
Bit
6
6
6
-
-
-
-
-
-
Reserved
The value read from these bits is always 0. Do not set these bits.
Audio Output Left Gain
Refer to Table 157 for gain value.
Reserved
The value read from these bits is always 0. Do not set these bits.
AT85C51SND3B1 and AT85C51SND3B2: Audio Input Line Preamplifier Gain
Refer to Table 161 for gain value.
AT85C51SND3B0: Reserved
The value read from this bit is always 0. Do not set this bit.
Audio Input Preamplifier Gain
Refer to Table 160 for gain value.
Reserved
The value read from these bits is always 0. Do not set these bits.
Channel Select DSEL Signal Output Polarity Bit
Set to output the left channel on high level of DSEL output (PCM mode).
Clear to output the left channel on the low level of DSEL output (I
Audio Data Size Bit
Set to select 32-bit data output format.
Clear to select 16-bit data output format.
5
5
5
-
-
-
AOLG4
CSPOL
4
4
4
-
AILPG -
AOLG3
DSIZE
3
3
3
OVERS1
AOLG2
AIPG2
2
2
2
OVERS0
AOLG1
AIPG1
1
1
1
7632D–MP3–01/07
2
S mode).
AOLG0
AIPG0
ADIEN
0
0
0
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