at85c51snd3 ATMEL Corporation, at85c51snd3 Datasheet - Page 237

• Manufacturer Part Number: at85c51snd3
• Description: At85c51snd3 Single-chip Digital Audio Decoder - Encoder With Usb 2.0 Interface
• Manufacturer: ATMEL Corporation

Registers
7632D–MP3–01/07
Table 256. LCDCON0 Register
LCDCON0 (1.96h) – LCD Control Register 0
Reset Value= 0000 0000b
Table 257. LCDCON1 Register
LCDCON1 (1.8Eh) – LCD Control Register 1
Number
Number
BUINV
SLW1
5-4
3-0
7-6
Bit
Bit
7
7
6
7
5
4
Mnemonic Description
Mnemonic Description
ADSUH1:0
ACCW3:0
RSCMD
LCYCW
SLW1:0
BUINV
LCIFS
LCIFS
SLW0
Bit
Bit
6
6
Busy Invert Active
Set to check busy bits selected in LCDBUM as active low.
Clear to check busy bits selected in LCDBUM as active high.
Interface Select Bit
Set to select 6800 interface type.
Clear to select 8080 interface type.
Address Setup/Hold
Address Setup and hold length in clock periods (from 1 to 4 clock periods).
Access Cycle Width
Access width in clock periods (from 1 to 16 clock periods).
In 8080 mode, corresponds to WR or RD low state.
In 6800 mode, corresponds to E high state.
Sleep Wait States
Busy check process enabled
Number of wait states between a read or write access and a busy check process
(from 1 to 4 clock periods).
Busy check process disabled
Number of wait states between two read or write accesses (from 1 to 4 clock
periods).
RS Command/Status
Set to output high level on LA0/LRS pin during busy check process.
Clear to output low level on LA0/LRS pin during busy check process.
This value depends on the LCD controller.
Deassertion Cycle Width
Set to program E or RD/WR signals deassertion time to the number of clock set
in ACCW3:0 bits.
Clear to let E or RD/WR signals deassertion time to the number of clock set in
ADSUH1:0 + SLW1:0.
ADSUH1
RSCMD
5
5
ADSUH0
LCYCW
4
4
ACCW3
LCYCT
3
3
ACCW2
LCEN
2
2
ACCW1
LCRD
1
1
ACCW0
LCRS
0
0
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