at85c51snd3 ATMEL Corporation, at85c51snd3 Datasheet - Page 182
at85c51snd3
Manufacturer Part Number
at85c51snd3
Description
At85c51snd3 Single-chip Digital Audio Decoder - Encoder With Usb 2.0 Interface
Manufacturer
ATMEL Corporation
Datasheet
1.AT85C51SND3.pdf
(271 pages)
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ECC Error Management
182
AT85C51SND3B
Figure 81. Nand Flash Write Protection Scheme
Since the NFWP signal state is part of the device status, the user can detect a fault be
reading it.
When an ECC error is detected, the ECCERRI flag is set in NFINT and the 4-byte ECC
error FIFO is updated. The FIFO content is read byte by byte using the NFERR register
as detailed in Table 200.
First byte of the FIFO returns a status if the error can or can not be corrected. If it can no
be corrected other 3-byte FIFO are cleared, If it can be corrected, the following 3 bytes
return the address of the byte in error within the page (2 bytes) and the address of the
bit in error within the byte (1 byte).
For example, if the byte read at offset 1921 (starting from 0) in a 2K page is E3 (wrong)
instead of A3:
•
•
•
Table 200. ECC Error Descriptor
Table 201. ECC Error Identification Byte
byte offset MSB will be 07h
byte offset LSB will be 81h
bit offset will be 06h
7
0
Offset
Block 0
FPB
LPB
0
1
2
3
6
0
FPB < LPB
Description
Error Identification Byte
Refer to Table 201 for information on byte content.
First 256-byte group of the sector
Byte offset
Second 256-byte group of the sector
Byte offset
Bit offset in the byte
Refer to Table 201 for information on byte content.
protected
5
0
Block 0
LPB
FPB
4
0
FPB > LPB
SHERRID1 SHERRID0 FHERRID1
protected
protected
3
2
Block 0
FPB
LPB
1
FPB = LPB
protected
Default
7632D–MP3–01/07
FHERRID0
0
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