at85c51snd3 ATMEL Corporation, at85c51snd3 Datasheet - Page 157

• Manufacturer Part Number: at85c51snd3
• Description: At85c51snd3 Single-chip Digital Audio Decoder - Encoder With Usb 2.0 Interface
• Manufacturer: ATMEL Corporation

Clock Controller
Data Converter
7632D–MP3–01/07
Figure 75. Audio DAC Interface Block Diagram
As soon as audio DAC interface is enabled by setting ADIEN bit in ADICON0, the mas-
ter clock generated by the clock generator (see Section “Clock Generator”) is output on
the OCLK pin which is the DAC over-sampling clock. The over-sampling ratio is defined
by OVERS1:0 bits in ADICON0 according to Table 164 and is selected depending on
the DAC capabilities.
Table 164. Audio DAC Interface Over-sampling Ratio
For DAC compatibility, the bit clock frequency is programmable for outputting 16 bits or
32 bits per channel using the DSIZE bit in ADICON0 (see Section "Data Converter",
page 157), and the word selection signal (DSEL) is programmable for outputting left
channel on low or high level according to CSPOL bit in ADICON0 as shown in
Figure 76.
Figure 76. DSEL Output Polarity
The data converter block converts the audio stream coming from the audio processor to
a serial format. For accepting all PCM formats and I
register are used to shift the data output point. As shown in Figure 77, these bits allow
MSB justification by setting JUST4:0 = 00000, LSB justification by setting JUST4:0 =
10000, I
tion by filling the low significant bits with logic 0.
Audio Data From
Audio Processor
CLOCK
2
OVERS1:0
S Justification by setting JUST4:0 = 00001, and more than 16-bit LSB justifica-
AUD
00
01
10
11
CSPOL = 0
CSPOL = 1
ADICON0.0
ADIEN
Over-sampling Ratio
Reserved
128 · F
256 · F
384 · F
OVERS1:0
ADICON0.2:1
S
S
S
Clock Controller
Left Channel
Left Channel
ADICON0.3
DSIZE
2
S format, JUST4:0 bits in ADICON1
Right Channel
Right Channel
ADICON1.4:0
Converter
JUST4:0
Data
ADICON0.4
CSPOL
0
1
OCLK
DCLK
DSEL
DDAT
157