at85c51snd3 ATMEL Corporation, at85c51snd3 Datasheet - Page 50
at85c51snd3
Manufacturer Part Number
at85c51snd3
Description
At85c51snd3 Single-chip Digital Audio Decoder - Encoder With Usb 2.0 Interface
Manufacturer
ATMEL Corporation
Datasheet
1.AT85C51SND3.pdf
(271 pages)
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Memory Space
Memory Segments
CODE Segment
DATA Segment
Lower 128 Bytes
50
AT85C51SND3B
The AT85C51SND3B derivatives implement an “all in one” 64K bytes of RAM split
between the three standard C51 memory segments:
•
•
•
To satisfy application needs in term of CODE and XDATA sizes, size and base address
of XDATA and CODE segments and base address of DATA segment can be dynami-
cally configured.
Figure 25 shows the memory space organization.
Figure 25. Memory Organization
The AT85C51SND3B executes up to 64K Bytes of program/code memory.
The AT85C51SND3B implements an additional 4K Bytes of on-chip boot ROM memory.
This boot memory is delivered programmed with a boot strap software allowing loading
of the application code from the Nand Flash Memory to the internal RAM. It also con-
tains a boot loader software allowing In-System Programming (ISP).
The DATA segment is mapped in two separate segments:
The lower 128 Bytes of RAM (see Figure 26) are accessible from address 00h to 7Fh
using direct or indirect addressing modes. The lowest 32 Bytes are grouped into 4
banks of 8 registers (R0 to R7). 2 bits RS0 and RS1 in PSW register (see Table 64)
select which bank is in use according to Table 63. This allows more efficient use of code
space, since register instructions are shorter than instructions that use direct address-
ing, and can be used for context switching in interrupt service routines.
CODE
DATA
XDATA
–
–
The lower 128 Bytes RAM segment
The upper 128 Bytes RAM segment
CPU
DFC
Bus
Bus
Secured Boot ROM
64K Bytes RAM
8K Bytes
XDATA
CODE
DATA
-
11FFFh
10000h
FFFFh
0000h
7632D–MP3–01/07
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