at85c51snd3 ATMEL Corporation, at85c51snd3 Datasheet - Page 78

• Manufacturer Part Number: at85c51snd3
• Description: At85c51snd3 Single-chip Digital Audio Decoder - Encoder With Usb 2.0 Interface
• Manufacturer: ATMEL Corporation

Data Flow Controller
CPU Interface
Clock Unit
Data Flow Descriptor
78
AT85C51SND3B
The Data Flow Controller (DFC) implemented in the AT85C51SND3B derivatives is the
multimedia data transfer manager. Up to two data transfers can be established through
two physical data channels between a source peripheral and a destination peripheral.
Figure 45 shows which peripherals are connected to the internal bus which are: the
CPU internal bus, the multimedia data bus and the DFC control bus.
Figure 45. DFC Internal Architecture
The DFC interfaces to the C51 core through the following special function registers:
DFCON the DFC control register, DFCSTA the channel status register, DFCCON the
channel control register, DFD0 and DFD1, the physical channel 0 and channel 1 data
flow descriptor registers and DFCRC the CRC data register.
T he DF C cl oc k i s gen er ate d bas ed on th e cl oc k ge nerat or a s det ail ed i n
Section “DFC/NFC Clock Generator”, page 31. Depending on the power mode (USB
powered or battery powered) and the throughput desired, different clock values may be
selected to control the data transfer. The DFC does not receive its system clock until
DFEN bit in DFCON is set, i.e. DFC enabled.
As shown in Table 91 the data flow is characterized by a 5-byte data flow descriptor: the
DFD composed of 4 fields. The data flow descriptor is written byte by byte to DFD0
(channel 0) or to DFD1 (channel 1). As soon as a DFD has been fully written, the chan-
nel is enabled and data flow transfer starts when both source and destination are ready
to send and receive data respectively.
CLOCK
DFC
CPU
DFC
DFCON.0
DFEN
Internal Bus
CPU
Control Bus
DFC
Multimedia
Data Bus
MMC
RAM
USB
AUP
NFC
SIO
7632D–MP3–01/07
PSI
SPI