at85c51snd3 ATMEL Corporation, at85c51snd3 Datasheet - Page 8
at85c51snd3
Manufacturer Part Number
at85c51snd3
Description
At85c51snd3 Single-chip Digital Audio Decoder - Encoder With Usb 2.0 Interface
Manufacturer
ATMEL Corporation
Datasheet
1.AT85C51SND3.pdf
(271 pages)
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Signals Description
System
8
AT85C51SND3B
Table 1. System Signal Description
Table 2. Ports Signal Description
Signal
Signal
P0.7:0
P1.7:0
P2.7:0
P3.4:0
P3.7:6
Name
Name
RST
ISP
Type Description
Type Description
I/O
I/O
I/O
I/O
I/O
I
Reset Input
Holding this pin low for 64 oscillator periods while the oscillator is
running resets the device. The Port pins are driven to their reset
conditions when a voltage lower than V
oscillator is running.
This pin has an internal pull-up resistor (R
to be reset by connecting a capacitor between this pin and V
Asserting RST when the chip is in Idle mode or Power-Down mode
returns the chip to normal operation.
In order to reset external components connected to the RST line a low
level 96-clock period pulse is generated when the watchdog timer
reaches its time-out period.
In System Programming
Assert this pin during reset phase to enter the in system programming
mode.
Port 0
P0 is an 8-bit bidirectional I/O port with internal pull-ups.
Port 1
P1 is an 8-bit bidirectional I/O port with internal pull-ups.
Port 2
P2 is an 8-bit bidirectional I/O port with internal pull-ups.
Port 3
P3 is a 7-bit bidirectional I/O port with internal pull-ups.
IL
is applied, whether or not the
RST
) which allows the device
SS
.
7632D–MP3–01/07
SDDAT3:0
Alternate
Alternate
Function
Function
SDCMD
UVCON
SDLCK
SDCLK
KIN3:0
SDINS
OCDT
LD7:0
MISO
MOSI
RXD
INT0
SCK
INT1
TXD
RTS
CTS
UID
SS
T0
-
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