at85c51snd3 ATMEL Corporation, at85c51snd3 Datasheet - Page 31

• Manufacturer Part Number: at85c51snd3
• Description: At85c51snd3 Single-chip Digital Audio Decoder - Encoder With Usb 2.0 Interface
• Manufacturer: ATMEL Corporation

X2 Feature
DFC/NFC Clock
Generator
7632D–MP3–01/07
Figure 19. System Clock Generator Block Diagram and Symbols
Table 26. System Clock Selection
Unlike standard C51 products that require 12 clock periods per machine cycle, the
AT85C51SND3B needs only 6 clock periods per machine cycle. This feature called the
“X2 feature” can be enabled using the X2 bit
AT85C51SND3B to operate in 6 or 12 clock periods per machine cycle. As shown in
Figure 19, both CPU and peripheral clocks are affected by this feature. Figure 20 shows
the X2 mode switching waveforms. After reset the standard mode is activated. In stan-
dard mode the CPU and peripheral clock frequency is the oscillator frequency divided by
2 while in X2 mode, it is the oscillator frequency.
Figure 20. Mode Switching Waveforms
In order to optimize the data transfer throughput between the DFC and the NFC, both
peripherals share the same clock frequency. The DFC and NFC clock generator block
diagram is shown in Figure 21 and is based on a frequency selector.
Frequency selection is done using DNFCKS2:0 bits in CKSEL (see Table 33) according
to Table 27.
Frequency is enabled by setting DNFCKEN bit in CKEN.
F
SYS
CLOCK
CLOCK
X2 bit
Clock
OSC
GEN
F
SYS
÷ 2
SYSCKS1:0
Audio Clock Symbol
00
01
10
11
CLOCK
STD Mode
AUD
24 MHz
30 MHz
40 MHz
SYSCKS1:0
CKSEL.1:0
00
01
10
11
Clock Selection (F
F
24 MHz
30 MHz
40 MHz
OSC
F
(default)
SYS
Peripheral Clock Symbol
÷
CLOCK
PER
2
SYS
X2 Mode
)
CKCON.0
X2
0
1
( 1 )
PCON.0
IDL
in CK CO N and al lows the
CPU Core Clock Symbol
CLOCK
CPU
Audio Controller
Clock
Peripheral
Clock
CPU Core
Clock
STD Mode
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