at85c51snd3 ATMEL Corporation, at85c51snd3 Datasheet - Page 209

• Manufacturer Part Number: at85c51snd3
• Description: At85c51snd3 Single-chip Digital Audio Decoder - Encoder With Usb 2.0 Interface
• Manufacturer: ATMEL Corporation

Write Data Sampling
7632D–MP3–01/07
detailed in following sections and differs depending on SA0 level. Table 235 shows the
addressing truth table. Figure 100 and Figure 101 show the read and write host cycles.
Table 231. PSI Addressing Truth Table
Figure 100. Host Read Waveforms
Figure 101. Host Write Waveforms
In order to be compliant with hosts depending on write cycle timing, a delay from SRW
signal assertion can be programmed for sampling data written by the host. This delay is
programmable from 0 to 7 peripheral clock periods using PSWS2:0 bits in PSICON. Fig-
ure 102 shows the write sampling delay waveform.
Depending on the system clock frequency, host may need to add wait states inside read
or write cycles.
SA0
SD7:0
SD7:0
1
1
0
0
SWR
SRD
SCS
SCS
SA0
SA0
SRD / SWR
Read
Write
Read
Write
Host reads the PSISTH register to get PSI status from both hardware and
software.
Host writes in the FIFO.
DFC transfer (PSI is destination)
Host reads data from the source peripheral through the FIFO.
CPU transfer
Host reads data from the FIFO.
DFC transfer (PSI is source)
Host writes data to the destination peripheral through the FIFO.
CPU transfer
Host writes data in the FIFO.
Read PSISTH
Data Write
Selection
Data Write
Read Data
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