at85c51snd3 ATMEL Corporation, at85c51snd3 Datasheet - Page 204
at85c51snd3
Manufacturer Part Number
at85c51snd3
Description
At85c51snd3 Single-chip Digital Audio Decoder - Encoder With Usb 2.0 Interface
Manufacturer
ATMEL Corporation
Datasheet
1.AT85C51SND3.pdf
(271 pages)
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AT85C51SND3B
Reset Value = 0000 0000b
Table 224. MMCON2 Register
MMCON2 (1.B3h) – MMC Control Register 2
Reset Value = 0000 0000b
Table 225. MMBLP Register
MMCON2 (1.B4h) – MMC Block Length LSB Register
Number
Number
BLEN7
FCK
4-3
2-1
Bit
Bit
2
1
0
7
7
6
5
0
7
DBSIZE1:0
Mnemonic Description
Mnemonic Description
DATD1:0
MMCEN
RXCEN
TXCEN
DATEN
BLEN6
DCR
DCR
CCR
FCK
Bit
Bit
6
6
Data Transfer Enable Bit
Set to enable data transmission or reception immediately or after response has
been received.
Cleared by hardware after the CRC reception in reception mode or after the busy
status if any in transmission mode.
Response Command Enable Bit
Set to enable the reception of a response following a command transmission.
Cleared by hardware when response is received.
Cleared by hardware when command is transmitted.
MMC Force Clock Bit
Set to enable the MCLK clock out permanently.
Clear to disable the MCLK clock and enable flow control.
Data Controller Reset Bit
Set to reset the data line controller in case of transfer abort, or to reset CRC16S
bit after an error occurs.
Cleared by hardware after the data line controller reset is achieved.
Command Controller Reset Bit
Set to reset the command line controller in case of transfer abort.
Cleared by hardware after the command line controller reset is achieved.
Data Bus Size
Refer to Table 220 for bits description.
Used to delay the data transmission after a response from 3 MMC clock periods
(all bits cleared) to 9 MMC clock periods (all bits set) by step of 2 MMC clock
periods.
MMC Clock Enable Bit
Set to enable the MMC clocks and activate the MMC controller.
Clear to disable the MMC clocks and freeze the MMC controller.
Command Transmission Enable Bit
Set to enable transmission of the command FIFO to the card.
Data Transmission Delay Bits
BLEN5
CCR
5
5
DBSIZE1
BLEN4
4
4
DBSIZE0
BLEN3
3
3
BLEN2
DATD1
2
2
DATD0
BLEN1
1
1
7632D–MP3–01/07
MMCEN
BLEN0
0
0
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