peb3456 Infineon Technologies Corporation, peb3456 Datasheet - Page 104

• Manufacturer Part Number: peb3456
• Description: Channelized T3 Termination With Ds3 Framer, M13 Multiplexer, T1/ E1 Framers And 256 Channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

several ways. The access via registers RSAW and XSAW, capable of storing the
information for a complete multiframe, and the most effective one is the access via the
receive/transmit FIFOS of the integrated signaling controller.
The extended S
positions. Any combination of S
completely sent out an “all ones” or flags will be transmitted. The continuous
transmission of a transparent bit stream, which is stored in the XFF.XFIFO, can be
enabled.
The access to and from the FIFOs is supported by status and interrupts.
S
Four consecutive received S
combinations. The TE3-CHATT can be programmed to detect any bit combination on
one S
register RCR2.SASSM. A valid S
corresponding status in register RSAW4 will be set. Register RSAW4 is from type “Clear
on Read”. With any change of state of the selected S
Valid’ interrupt vector will be generated.
After detecting an HDLC flag, byte sampling is stopped, the receive status byte marking
a BOM frame is stored in the receive FIFO and a ’Receive Message End’ interrupt vector
is generated.
Byte sampling may be stopped by deactivating the BOM receiver (RCR1.BRAC). In this
case the receive status byte marking a BOM frame is added, a ’Receive Message End’
interrupt vector is generated and HDLC mode is entered.
BOM Filter Mode
In BOM filter mode the received BOM data is validated and then filtered. If same valid
BOM pattern is received for 7 out of 10 patterns, then BOM data is written to the receive
FIFO along with the status byte indicating that filtered BOM data was received.
Filtered BOM mode will be exited if one of the following conditions occurs:
• 4 valid BOM patterns are consecutively received but none of these equals the BOM
• 4 times idle pattern is received.
• A HDLC flag is received.
4.8.4
The TE3-CHATT supports the S
stream as well as HDLC frames where the signaling controller automatically processes
the HDLC protocol.
Data written to the transmit FIFO will subsequently be transmitted in the selected S
Data Sheet
a
-Bit Detection according to ETS 300233
data received earlier.
a
-bit out of S
S
a
-bit Access
a
-bit access gives the opportunity to transmit/receive a transparent bit
a4
through S
a
-bits are checked on the by ETS 300233 defined S
a8
. Enabling of specific bit combination can be done via
a
a
-bit combination must occur three times in a row. The
a
-bit signaling of time-slot 0 of the T1/E1 signals in
-bits can be selected. After the data have been
104
a
-bit combinations a ’SSM Data
Functional Description
PEB 3456 E
05.2001
a
a
-bit
-bit