peb3456 Infineon Technologies Corporation, peb3456 Datasheet - Page 143

• Manufacturer Part Number: peb3456
• Description: Channelized T3 Termination With Ds3 Framer, M13 Multiplexer, T1/ E1 Framers And 256 Channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

RSDL
TSDL
LPCS
SEC
N
4.13.2.4 DS3, DS2 and Test Unit Interrupts
Note: The DS3, DS2 and test unit interrupts are seperated by the INFO field (bits 4
DS3 Interrupts Type 0
•
DS3 Interrupts Type 1
•
CLKS
Data Sheet
r
LAST
LAST
15
15
through 0).
14
14
0
1
AIC
13
13
0
DS3 Clock Status
The ‘DS3 Clock Status’ interrupt vector is generated whenever the TE3-
CHATT detects a change in the transmit clock or the receive clock, i.e.
clock is activated/deactivated. The actual status of the clock is shown in
D3RSTAT.LRXC and D3RSTAT.LTXC.
Receive Spare Data Link Transfer Buffer Full
The ‘Receive Spare Data Link Transfer Buffer Full’ interrupt vector is
generated when the receive spare data link buffer needs to be emptied.
Transmit Spare Data Link Transfer Buffer Empty
The ‘Transmit Spare Data Link Transfer Buffer Empty’ interrupt vector is
generated when the transmit spare data link buffer needs to be filled.
Loopback Code Status
The ‘Loopback Code Status’ interrupt vector is generated whenever the
TE3-CHATT detects a change in the received loopback codes. Actual
loopback codes can be found in register D3RLPCS.
1 Second Interrupt
The ‘1 Second Interrupt’ is generated every second.
Received new N
The ‘Received new N
TE3-CHATT detects a change in the NA overhead bits and when its
state is persistent for at least three multiframes.
CLKS RSDL TSDL LPCS SEC
XBIT IDLES AISS REDS LOSS FAS
12
12
11
11
10
10
r
-Bit
9
9
r
-Bit’ interrupt vector is generated whenever the
8
8
143
N
7
7
r
6
6
10
10
B
B
5
5
4
4
Functional Description
00111
00111
PEB 3456 E
H
H
05.2001
0
0