peb3456 Infineon Technologies Corporation, peb3456 Datasheet - Page 245

• Manufacturer Part Number: peb3456
• Description: Channelized T3 Termination With Ds3 Framer, M13 Multiplexer, T1/ E1 Framers And 256 Channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

IF
Q8..Q0
Data Sheet
as LINT changes from an inactive to an active state the interrupt pin
INTA will be asserted.
Note: This bit does not clear by writing a ’1’. This bit is set as long as
0
1
Interrupt FIFO
This bit indicates that there is an interrupt vector stored in the internal
interrupt FIFO. The IF interrupt is available if the interrupt pin LINT is
switched to input mode (INTCTRL.ID = ’1’) and when the interrupt mask
GMASK.IF is set to ’0’.
Note: This bit does not clear by writing a ’1’. This bit is set as long as an
0
1
Interrupt Queue 8..0
On reads each bit flags one or more interrupt vectors that have been
written to the corresponding interrupt queue. If one of the bits is set and
the same bit is not masked in register GMASK, the interrupt pin INTA will
be asserted. A bit is cleared, when an ’1’ is written to the specific bit.
0
1
the interrupt pin LINT is asserted.
LINT not asserted.
LINT asserted.
interrupt vector is stored in the interrupt FIFO.
No Interrupt vector in interrupt FIFO.
Interrupt vector stored in internal interrupt FIFO.
No interrupt vector written.
Read: One or more interrupt vectors have been written to
interrupt queue.
Write: Clear bit
245
Register Description
PEB 3456 E
05.2001