peb3456 Infineon Technologies Corporation, peb3456 Datasheet - Page 107

• Manufacturer Part Number: peb3456
• Description: Channelized T3 Termination With Ds3 Framer, M13 Multiplexer, T1/ E1 Framers And 256 Channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

PEB 3456 E
Functional Description
•
Receive frame (79 bytes)
32 bytes
32 bytes
15 bytes
FDL channel
Local Bus
Interface
RD
RD
RD
RD
RD
32 bytes
32 bytes
RBC
15 bytes
status
RPF
RPF
RME
RMC
RMC
RMC
Figure 4-12 Interrupt Driven Reception Sequence Example
Transmit FIFO
In the transmit direction after checking the transmit FIFO status by polling the transmit
FIFO write enable bit (PSR.XFW) or after a ’Transmit Pool Ready’ (XPR) interrupt vector,
up to 32 bytes may be written to the transmit FIFO (bit field XFF.XFIFO) by the CPU.
Transmission of a frame can be started by issuing a ’Transmit Transparent Frame’ (XTF)
or ’Transmit HDLC Frame’ (XHF) command via register HND. If the transmit command
does not include a ’Transmit Message End’ indication (HND.XME), the signalling
controller will repeatedly request for the next data block by means of a XPR interrupt
vector as soon as the transmit FIFO becomes free. This process will be repeated until
the local CPU writes the last bytes to the transmit FIFO. The end of message is then
indicated per HND.XME command, after which frame transmission is finished correctly
by appending the CRC and closing flag sequence. Consecutive frames may share a flag
(enabled via bit XCR1.SF) or may be transmitted as back-to-back frames, if service of
transmit FIFO is quick enough. In case that no more data is available in the transmit FIFO
prior to the arrival of HND.XME, the transmission of the frame is terminated with an abort
sequence and the CPU is notified via a ’Transmit Data Underrun’ interrupt vector (XDU).
The frame may also be aborted per software by setting the XAB bit in the handshake
register HND.
Data Sheet
107
05.2001