peb3456 Infineon Technologies Corporation, peb3456 Datasheet - Page 22

• Manufacturer Part Number: peb3456
• Description: Channelized T3 Termination With Ds3 Framer, M13 Multiplexer, T1/ E1 Framers And 256 Channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

Optionally the device supports unchannelized DS3 applications. An internal bit error rate
tester can be attached to different test points and provides flexible PRBS and fixed
• Support of 256 bidirectional channels, which can be assigned arbitrarily to a maximum
• Concatenation of any, not necessarily consecutive, time slots to logical channels on
• Provides 32kB data buffer in transmit direction and 12kB data buffer in receive
• Integrates 28T1/21E1 framers (frame alignment function) and 28T1/21E1 signalling
• Integrates a DS2/DS3 multiplexer and framer
• Remote loopbacks selectable for either DS3 signal, DS2 signal or T1/E1 signal/
• System interface is a PCI 32 bit, 66 MHz Rev. 2.1 compliant bus interface, which
• Integrates a local microprocessor master and slave interface (demultiplexed 16 bit
• For debugging purposes optional access to the framer and signalling controller
• JTAG boundary scan according to IEEE1149.1 (5 pins).
• 0.25 µm, 2.5V core technology
• I/Os are 3.3V tolerant and have 3.3V driving capability
• Package P-BGA 388 (35mm x 35mm; pitch 1.27mm)
1
The TE3-CHATT is a highly integrated protocol controller that implements HDLC, PPP
and transparent (TMA) protocol processing for 256 channels as well as frame alignment
for up to 28 T1 signals or 21 E1 signals. An integrated M13 multiplexer together with a
DS3 framer concentrates the data links for direct connection to a DS3 line interface unit.
pattern tests. An on-chip data management unit is optimized to transfer data packets via
a PCI interface by minimizing the bus load.
Note: The TE3-CHATT does not contain DS3 Line Interface Units.
1.1
• Protocol processing on a channelized or unchannelized DS3 link for frame relay or
• Direct connection to DS3 line interface unit or DS3 to STS-1 mapper
Data Sheet
router applications
of 28 links, for HDLC, PPP or transparent mode (TMA) processing
each physical link. Supports DS0, fractional T1/E1 or T1/E1 channels
direction
controllers
payload
supports configuration of subsystem ID / subsystem vendor ID via a serial EEPROM
interface. PCI bus interface can be operated in the range of 33 MHz to 66 MHz
address and data bus in Intel mode or Motorola mode) which allows access to the
local bus via the PCI bus or which can communicate with a PCI host processor
through an on-chip mailbox
functions via the PCI interface
TE3-CHATT Overview
General Features
22
TE3-CHATT Overview
PEB 3456 E
05.2001