peb3456 Infineon Technologies Corporation, peb3456 Datasheet - Page 220

• Manufacturer Part Number: peb3456
• Description: Channelized T3 Termination With Ds3 Framer, M13 Multiplexer, T1/ E1 Framers And 256 Channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

CONF3
Configuration Register 3
Access
Address
Reset Value
TPBL
MINFL
Data Sheet
31
15
0
0
0
0
13
0
: read/write
: 048
: 00090000
Transmit Packet Burst Length
This bit field is a coding for the maximum burst length on PCI bus, when
data management unit fetches transmit packets. Please refer to
7 "Threshold Codings" on Page 209
code and maximum burst length.
Minimum Frame Length
Only valid for those channel which have bit CSPEC_MODE_REC.SFDE
set. MINFL sets the minimum frame length in bytes (payload bytes and
CRC bytes) for frames which will be forwarded to system memory. If
enabled the receive buffer will drop frames which are smaller or equal to
the programmed value MINFL to avoid wasting of PCI bandwidth in case
of error conditions. The small frame check is disabled, if MINFL is set to
zero.
Note: Since the receive packets will be dropped inside the receive
0
H
buffer, the receive packet threshold CSPEC_BUFFER.RTC has
to be greater than MINFL/4 in order to work properly.
MINFL(5:0)
0
H
0
0
0
8
220
0
0
0
0
0
0
for correspondence between
0
0
Register Description
19
0
TPBL(3:0)
0
PEB 3456 E
0
Table 8-
05.2001
16
0
0