peb3456 Infineon Technologies Corporation, peb3456 Datasheet - Page 123

• Manufacturer Part Number: peb3456
• Description: Channelized T3 Termination With Ds3 Framer, M13 Multiplexer, T1/ E1 Framers And 256 Channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

PEB 3456 E
Functional Description
Mailbox interrupts and layer one interrupts are handled via an internal interrupt FIFO
which is connected to the local bus interrupt pin LINT (normal operation). Additionally the
interrupts stored in the internal interrupt FIFO can be notified via the PCI interrupt pin
INTA.
The TE3-CHATT also provides the capability to bridge the local bus interrupt LINT to the
PCI bus.
4.13.1
Layer Two interrupts
All channel interrupts, port interrupts and system interrupts are written in form of interrupt
vectors to interrupt queues.
Each interrupt vector has an interrupt source. An interrupt source is either a channel, the
port handler or certain device functions (system interrupts). After reset no interrupt vector
is generated since port and system interrupts are masked and channels are in their idle
state.
Each interrupt source forwards its interrupt vector to the interrupt controller, together with
the information in which interrupt queue the vector should be forwarded. The interrupt
controller moves the interrupt vector to the selected interrupt queue. Channel interrupts
can optionally be forwarded to a dedicated high priority interrupt queue (interrupt queue
seven). A programmable interrupt queue high priority mask determines channel
interrupts, which shall be forwarded into the high priority interrupt queue instead of
queueing them in the selected interrupt queue. This function is available for each
interrupt queue and allows to queue important interrupt conditions in the high priority
queue.
Data Sheet
123
05.2001