peb3456 Infineon Technologies Corporation, peb3456 Datasheet - Page 370

• Manufacturer Part Number: peb3456
• Description: Channelized T3 Termination With Ds3 Framer, M13 Multiplexer, T1/ E1 Framers And 256 Channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

PSR
Port Status register
Access
Address
Reset Value
XRA
XFW
RBC
SMODE
Data Sheet
15
XRA XFW
14
13
: read
: 06
: 0000
Transmit Repeat Active
This bit indicates that the transmit signalling controller is operating in
repeat mode.
0
1
Transmit FIFO Write Enable
This bit indicates that data can be written to XFF.XFIFO. This bit is for
polling use with the same meaning as the ’Transmit Pool Ready’
interrupt vector.
Receive Byte Count
This bit field indicates the amount of data stored in the receive FIFO.
Valid after a ’Receive Message End’ interrupt vector is generated.
Receive byte count will be cleared, when a ’Receive Message Clear’
command is executed via register HND. A zero byte count in
combination with a ‘Receive Pool Full’ or ’Receive Message End’
interrupt vector means that 32 bytes are available in the receive FIFO.
Receiver Status Mode
This bit indicates the status of the receive signalling controller. If BOM
mode is selected via bit RCR1.BRM the receiver switches automatically
between HDLC mode and BOM mode.
10
01
Other Reserved
B
B
12
H
H
Normal operation
Repeat operation
HDLC mode
BOM mode
RBC(4:0)
8
370
SMODE(1:0) BRFO
7
6
5
4
Register Description
STAT(4:0)
PEB 3456 E
05.2001
0