peb3456 Infineon Technologies Corporation, peb3456 Datasheet - Page 106

• Manufacturer Part Number: peb3456
• Description: Channelized T3 Termination With Ds3 Framer, M13 Multiplexer, T1/ E1 Framers And 256 Channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

After the received data has been read from the FIFO, the receive FIFO can be released
by the CPU by issuing a ’Receive Message Complete’ (HND.RMC) command. The CPU
has to process a ’Receive Pool Full’ interrupt vector and issue the ’Receive Message
Complete’ command before the second page of the FIFO becomes full. Otherwise a
’Receive Data Overflow’ condition will occur. This time is dependent on the threshold
programmed (smaller threshold results in shorter time).
Data Sheet
SMODE
BRFO
STAT
Receiver Status Mode
This bit indicates the type of data received.
10
01
BOM Receive FIFO Overflow
0
1
Receive FIFO Status
This bit field reports the status of the data stored in the receive FIFO.
B
B
00000
00001
00010
00011
00100
00101
HDLC data
BOM data
No overflow
Receive FIFO overflow
B
B
B
B
B
B
HDLC mode
Valid HDLC Frame
Receive Data Overflow
Receive Abort
Not Octet
CRC Error
Channel Off
106
BOM MODE
BOM Filtered data declared
BOM data available
BOM End
BOM filtered data undeclared
BOM header error (ISF, incorrect
synchronization format)
Functional Description
PEB 3456 E
05.2001