peb3456 Infineon Technologies Corporation, peb3456 Datasheet - Page 51

• Manufacturer Part Number: peb3456
• Description: Channelized T3 Termination With Ds3 Framer, M13 Multiplexer, T1/ E1 Framers And 256 Channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

The local bus interface provides a switchable Intel-style or Motorola-style processor
interface.
M23 multiplexer/demultiplexer and DS3 framer
In channelized operating modes the M23 multiplexer/demultiplexer maps/demaps seven
DS2 signals into/from M13 asynchronous format or C-bit parity format. In unchannelized
mode one logical input stream is mapped into the information bits of the DS3 stream
according to ANSI T1.107. The DS3 framer performs frame and multiframe alignment in
receive direction and inserts the frame and multiframe alignment bits. Performance
monitors provide for counting of framing bit errors, parity errors, CP-bit errors, far end
block errors, excessive zeroes or line code violations. The framer detects loopback
requests and allows insertion of loopback requests under microprocessor control.
M12 multiplexer/demultiplexer and DS2 framer
The M12 multiplexer/demultiplexer operates in two modes. It maps either 28 T1 signals
or 21 E1 signals into/from seven ANSI T1.107 or ITU-T G.747 compliant DS2 signals. It
performs inversion of the second and fourth DS1 signal. The DS2 framer performs frame
and multiframe alignment in receive direction and vice versa inserts the framing bits
according to ANSI T1.107 or ITU-T G.704. It detects loopback requests or enables
insertion of loopback requests under microprocessor control.
T1/E1 framer
Synchronization is achieved with the on-chip framing function. T1/E1 mode is supported
for up to 28 ports. Once the framer achieved synchronization for a line, that is the frame
alignment information in the incoming bit stream has been identified correctly, it informs
the port interface and the facility data link about the frame position. In transmit direction
the framing bits are inserted according to T1 F4 format, T1 SF (F12) format, T1 ESF
(F24) format, E1 doubleframe format or E1 CRC-4 multiframe format. Performance
monitors provide for counting framing errors, CRC errors, block errors, E-bit errors or
PRBS bit errors. The framer detects loopback requests and allows insertion of loopback
requests or pseudo-random bit sequences under microprocessor control.
PCI interface directly. Thus the device could also be operated without a local
microprocessor connected to it, e.g. for debugging purposes. It is NOT possible to
access the configuration bus I and therefore the ’HDLC’ registers or the PCI bridge from
the local bus.
Local bus interface
The local bus interface provides access between the local microprocessor and the on-
chip configuration bus II, in order to access the registers of the on-chip M13 multiplexer,
DS2/DS3 framer, T1/E1 framer, the registers of the signalling controller and the mailbox.
Data Sheet
51
General Overview
PEB 3456 E
05.2001