peb3456 Infineon Technologies Corporation, peb3456 Datasheet - Page 239

• Manufacturer Part Number: peb3456
• Description: Channelized T3 Termination With Ds3 Framer, M13 Multiplexer, T1/ E1 Framers And 256 Channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

SIQM
IQIA
Interrupt Queue Indirect Access Register
Access
Address
Reset Value
DBG
Data Sheet
31
15
0
0
0
0
0
0
: read/write
: 0E0
: 00000000
Debug
This bit selects the debug mode of the interrupt controller. When DEBUG
is set, the actual values of interrupt queue base address, interrupt queue
length and high priority interrupt queue mask of queue Q are copied to
register IQBA, IQL and IQMASK. The value can be read with a following
access to these registers.
Note: Setting DEBUG is only allowed, if neither SIQBA, SIQL and SIQM
0
1
Set High Priority Interrupt Queue Mask
This bit field enables setup of the high priority interrupt queue mask of
queue Q. The value to be programmed has to be configured via register
IQMASK prior to a write access to this bit.
0
1
0
0
H
are set.
No operation
Enable debug mode.
No operation
Set high priority mask.
0
0
H
0
0
0
0
0
0
239
0
0
0
0
0
0
0
0
Register Description
DBG SIQM SIQL SIQBA
19
3
18
Q(3:0)
PEB 3456 E
17
05.2001
16
0