peb3456 Infineon Technologies Corporation, peb3456 Datasheet - Page 148

• Manufacturer Part Number: peb3456
• Description: Channelized T3 Termination With Ds3 Framer, M13 Multiplexer, T1/ E1 Framers And 256 Channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

transfer, so IRDY is deasserted on clock 7, and FRAME stays asserted. Only when IRDY
is asserted can FRAME be deasserted, which occurs on clock 8.
•
Figure 5-1
5.1.2
The transaction starts when FRAME is activated (clock 1 in Figure 5-2). A write
transaction is similar to a read transaction except no turnaround cycle is required
following the address phase. In the example, the first and second data phases complete
with zero wait cycles. The third data phase has three wait cycles inserted by the target.
Both initiator and target insert a wait cycle on clock 5. In the case where the initiator
inserts a wait cycle (clock 5), the data is held on the bus, but the byte enables are
withdrawn. The last data phase is characterized by IRDY being asserted while the
FRAME signal is deasserted. This data phase is completed when TRDY goes active
(clock 8).
Data Sheet
DEVSEL
FRAME
TRDY
C/BE
IRDY
CLK
AD
PCI Write Transaction
PCI Read Transaction
1
Command
Address
Address
phase
2
phase
Data
3
Data 1
4
Bus transaction
148
phase
BE's
Data
5
Data 2
6
Data 3
Interface Description
phase
Data
7
PEB 3456 E
8
05.2001