peb3456 Infineon Technologies Corporation, peb3456 Datasheet - Page 125

• Manufacturer Part Number: peb3456
• Description: Channelized T3 Termination With Ds3 Framer, M13 Multiplexer, T1/ E1 Framers And 256 Channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

nine interrupt queues can be masked. In this case the interrupt pin INTA is not asserted,
but the interrupt vector is still written into the assigned interrupt queue.
An interrupt queues is a reserved memory locations in system memory. The TE3-CHATT
supports up to eight interrupt queues which are organized in form of ring buffers with a
programmable start address and a programmable size per interrupt queue. Additionally
there is one fixed sized command interrupt queue where command interrupts are stored.
The size of this queue is two times 256 DWORDs (Figure 4-18).
•
Figure 4-18 Interrupt Queue Structure in System Memory
4.13.1.1 General Interrupt Vector Structure
Each interrupt vector is 32 bit wide and contains several subfields, which indicate the
interrupt group and depend on the interrupt group the interrupt information. Bit 31 of the
interrupt vector is generally set to ’1’ by the TE3-CHATT and allows the system CPU to
clear the bit in order to mark processed interrupts.
Table 4-15
Data Sheet
31
15
1
IQBA+4
IQBA
TYPE(1:0) STYPE(1:0)
30
H
Channel, Port and System
Interrupt Queue
29
Interrupt Vector IQL*16
Interrupt Vector Structure
Interrupt Vector 3
Interrupt Vector 2
Interrupt Vector 1
28
27
26
QUEUE(2:0)
INT(23:0)
24
125
23
IQBA+4
IQBA
H
Command Interrupt Queue
Note: IV = Interrupt Vector
Channel 255: Transmit Command IV
Channel 255: Receive Command IV
Channel 0: Transmit Command IV
Channel 1: Receive Command IV
Channel 0: Receive Command IV
INT(23:0)
Functional Description
PEB 3456 E
05.2001
16
0