peb3456 Infineon Technologies Corporation, peb3456 Datasheet - Page 368

• Manufacturer Part Number: peb3456
• Description: Channelized T3 Termination With Ds3 Framer, M13 Multiplexer, T1/ E1 Framers And 256 Channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

XCR2
Transmit Channel Configuration Register 2
Access
Address
Reset Value
IFTF
SA8E..SA4E
SMF
T1E1
Data Sheet
15
0
0
0
: read/write
: 04
: 0000
Interframe Time Fill
This bit determines the interframe time of the transmit signalling
controller.
0
1
S
Setting one of the bits switches between normal S
access of the selected bits.
0
1
Select CRC-4 Multiframe Format
This bit switches between doubleframe and multiframe format.
E1
0
1
T1/E1 Mode Selection
This bit switches the receive signalling controller into T1 or E1 mode.
0
1
a
-bit Signalling Enable
0
H
H
Interframe time fill is 7E
Interframe time fill is FF
Enable S
Enable protocol access (HDLC, transparent). Selected bits will
be combined for protocol data transmission.
Select doubleframe format.
Select CRC-4 multiframe format.
Select T1 mode.
Select E1 mode.
0
0
a
-bit access via register XSAW1-3.
0
8
0
368
IFTF SA8E SA7E SA6E SA5E SA4E SMF T1E1
7
H
H
.
.
6
5
4
a
Register Description
-bit access or protocol
3
2
PEB 3456 E
1
05.2001
0