SAF1562HL NXP [NXP Semiconductors], SAF1562HL Datasheet - Page 50

• Manufacturer Part Number: SAF1562HL
• Description: Hi-Speed Universal Serial Bus PCI Host Controller
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
SAF1562_1
Product data sheet
11.1.16 HcFmNumber register
[1]
Table 71.
Address: Value read from func0 or func1 of address 10h + 38h
This register is a 16-bit counter, and the bit allocation is given in
timing reference among events happening in the Host Controller and the HCD. The HCD
may use the 16-bit value specified in this register and generate a 32-bit frame number,
without requiring frequent access to the register.
Table 72.
Address: Value read from func0 or func1 of address 10h + 3Ch
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31
30 to 14
13 to 0
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
Symbol
FRT
reserved
FR[13:0]
HcFmRemaining - Host Controller Frame Remaining register bit description
HcFmNumber - Host Controller Frame Number register bit allocation
R/W
R/W
R/W
R/W
R/W
15
31
23
15
0
7
0
0
0
0
reserved
reserved
Description
Frame Remaining Toggle: This bit is loaded from FIT (bit 31 of
HcFmInterval) whenever FR[13:0] reaches 0. This bit is used by the HCD
for the synchronization between FI[13:0] (bit 13 to bit 0 of HcFmInterval)
and FR[13:0].
-
Frame Remaining: This counter is decremented at each bit time. When it
reaches 0, it is reset by loading the FI[13:0] value specified in HcFmInterval
at the next bit time boundary. When entering the USBOPERATIONAL state,
the Host Controller reloads the content with FI[13:0] of HcFmInterval and
uses the updated value from the next SOF.
Rev. 01 — 7 February 2007
R/W
R/W
R/W
R/W
R/W
[1]
[1]
14
30
22
14
0
6
0
0
0
0
R/W
R/W
R/W
R/W
R/W
13
29
21
13
0
5
0
0
0
0
Hi-Speed Universal Serial Bus PCI Host Controller
R/W
R/W
R/W
R/W
R/W
12
28
20
12
0
4
0
0
0
0
reserved
reserved
FR[7:0]
R/W
R/W
R/W
R/W
R/W
[1]
[1]
11
27
19
11
0
3
0
0
0
0
FR[13:8]
FN[13:8]
R/W
R/W
R/W
R/W
R/W
10
26
18
10
2
0
0
0
0
0
Table
SAF1562
72. It provides a
© NXP B.V. 2007. All rights reserved.
R/W
R/W
R/W
R/W
R/W
25
17
9
0
1
0
0
0
9
0
R/W
R/W
R/W
R/W
R/W
50 of 97
24
16
8
0
0
0
0
0
8
0