SAF1562HL NXP [NXP Semiconductors], SAF1562HL Datasheet - Page 29

• Manufacturer Part Number: SAF1562HL
• Description: Hi-Speed Universal Serial Bus PCI Host Controller
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
SAF1562_1
Product data sheet
8.2.3.6 Data register
Table 38.
Address: Value read from address 34h + 6h
Table 39.
The Data register is an optional, 1 B register that provides a mechanism for the function to
report state dependent operating data, such as power consumed or heat dissipated.
Table 40
Table 40.
Address: Value read from address 34h + 7h
Legend: * reset value
Bit
7
6
5 to 0
Originating device’s
bridge PM state
D0
D1
D2
D3
D3
Bit
7 to 0 DATA[7:0] R
hot
cold
Symbol
Symbol
BPCC_EN
B2_B3#
reserved
shows the bit description of the register.
PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions register bit
description
PCI bus power and clock control
Data register bit description
Access Value
Description
Bus Power/Clock Control Enable:
1 — Indicates that the bus power or clock control mechanism as defined in
Table 39
0 — Indicates that the bus or power control policies as defined in
are disabled
When the Bus Power or Clock Control mechanism is disabled, the bridge’s
PMCSR Power State (PS) field cannot be used by the system software to
control the power or clock of the bridge’s secondary bus.
B2/B3 support for D3
to occur as a direct result of programming the function to D3
1 — Indicates that when the bridge function is programmed to D3
secondary bus’s PCI clock will be stopped (B2)
0 — Indicates that when the bridge function is programmed to D3
secondary bus will have its power removed (B3)
This bit is only meaningful if bit 7 (BPCC_EN) is logic 1.
-
Secondary bus
PM state
B0
B1
B2
B2, B3
B3
Rev. 01 — 7 February 2007
00h*
is enabled
Description
DATA: This register is used to report the state dependent
data requested by the D_S field of the PMCSR register.
The value of this register is scaled by the value reported by
the DS field of the PMCSR register.
Hi-Speed Universal Serial Bus PCI Host Controller
Resultant actions by bridge
(either direct or indirect)
none
none
clock stopped on secondary bus
clock stopped and PCI V
bus (B3 only); for definition of B2_B3#, see
none
hot
: The state of this bit determines the action that is
CC
removed from secondary
SAF1562
© NXP B.V. 2007. All rights reserved.
hot
.
Table 38
Table 39
hot
hot
, its
, its
29 of 97