SAF1562HL NXP [NXP Semiconductors], SAF1562HL Datasheet - Page 27

• Manufacturer Part Number: SAF1562HL
• Description: Hi-Speed Universal Serial Bus PCI Host Controller
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
SAF1562_1
Product data sheet
Table 35.
[1]
[2]
Table 36.
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
15
14 and 13 DS[1:0]
12 to 9
Address: Value read from address 34h + 4h
Address: Value read from address 34h + 4h
Sticky bit, if the function supports PME# from D3
system boot; X is 0 if the function does not support PME# from D3
The reserved bits should always be written with the reset value.
PMCSR - Power Management Control/Status register bit allocation
PMCSR - Power Management Control/Status register bit description
Symbol
PMES
D_S[3:0]
PMES
R/W
R/W
X
15
7
0
[1]
Description
PME Status: This bit is set when the function normally asserts the PME#
signal independent of the state of the PMEE bit. Writing logic 1 to this bit
clears it and causes the function to stop asserting PME#, if enabled.
Writing logic 0 has no effect. This bit defaults to logic 0, if the function does
not support the PME# generation from D3
PME# generation from D3
cleared by the operating system each time the operating system is initially
loaded.
Data Scale: This two-bit read-only field indicates the scaling factor when
interpreting the value of the Data register. The value and meaning of this
field vary, depending on which data value is selected by the D_S field. This
field is a required component of the Data register (offset 7) and must be
implemented, if the Data register is implemented. If the Data register is not
implemented, this field must return 00b when PMCSR is read.
Data_Select: This four-bit field selects the data that is reported through the
Data register and the D_S field. This field is a required component of the
Data register (offset 7) and must be implemented, if the Data register is
implemented. If the Data register is not implemented, this field must return
00b when PMCSR is read.
Rev. 01 — 7 February 2007
R/W
14
R
0
6
0
DS[1:0]
R/W
13
R
0
5
0
reserved
Hi-Speed Universal Serial Bus PCI Host Controller
R/W
R/W
[2]
cold
12
0
4
0
cold
, then X is indeterminate at the time of initial operating
, then this bit is sticky and must be explicitly
R/W
R/W
11
0
3
0
D_S[3:0]
cold
cold
.
. If the function supports the
R/W
R/W
10
0
2
0
SAF1562
© NXP B.V. 2007. All rights reserved.
R/W
R/W
9
0
1
0
PS[1:0]
PMEE
R/W
R/W
X
27 of 97
8
0
0
[1]