SAF1562HL NXP [NXP Semiconductors], SAF1562HL Datasheet - Page 23

• Manufacturer Part Number: SAF1562HL
• Description: Hi-Speed Universal Serial Bus PCI Host Controller
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
SAF1562_1
Product data sheet
8.2.2.2 FLADJ register
8.2.2.3 PORTWAKECAP register
Table 26.
Legend: * reset value
This feature is used to adjust any offset from the clock source that generates the clock that
drives the SOF counter. When a new value is written to these six bits, the length of the
frame is adjusted. The bit allocation of the Frame Length Adjustment (FLADJ) register is
given in
Table 27.
[1]
Table 28.
Port Wake Capability (PORTWAKECAP) is a 2 B register used to establish a policy about
which ports are for wake events; see
correspond to a physical port implemented on the current EHCI controller. Logic 1 in a bit
position indicates that a device connected below the port can be enabled as a wake-up
device and the port may be enabled for disconnect or connect, or overcurrent events as
wake-up events. This is an information only mask register. The bits in this register do not
Bit
7 to 0
Bit
Symbol
Reset
Access
Bit
7 and 6
5 to 0
The reserved bits should always be written with the reset value.
Table
Symbol
reserved
FLADJ[5:0]
SBRN - Serial Bus Release Number register (address 60h) bit description
FLADJ - Frame Length Adjustment register (address 61h) bit allocation
FLADJ - Frame Length Adjustment register (address 61h) bit description
Symbol
SBRN[7:0] R
R/W
7
0
27.
reserved
Rev. 01 — 7 February 2007
R/W
[1]
Access
Description
-
Frame Length Timing Value: Each decimal value change to this register
corresponds to 16 high-speed bit times. The SOF cycle time—number of
SOF counter clock periods to generate a SOF micro frame length—is
equal to 59488 + value in this field. The default value is decimal 32 (20h),
which gives a SOF cycle time of 60000.
6
0
Value
20h*
FLADJ value
R/W
5
1
31 (1Fh)
62 (3Eh)
63 (3Fh)
32 (20h)
0 (00h)
1 (01h)
2 (02h)
Hi-Speed Universal Serial Bus PCI Host Controller
Table
:
:
Description
Serial Bus Specification Release Number: This
register value is to identify Serial Bus Specification
Rev. 2.0. All other combinations are reserved.
R/W
29. Bit positions 15 to 1 in the mask
4
0
R/W
3
0
FLADJ[5:0]
R/W
2
0
SOF cycle time
(480 MHz)
59488
59504
59520
59984
60000
60480
60496
SAF1562
© NXP B.V. 2007. All rights reserved.
:
:
R/W
1
0
R/W
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0
0