SAF1562HL NXP [NXP Semiconductors], SAF1562HL Datasheet - Page 63

• Manufacturer Part Number: SAF1562HL
• Description: Hi-Speed Universal Serial Bus PCI Host Controller
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
SAF1562_1
Product data sheet
11.2.3 HCCPARAMS register
The Host Controller Capability Parameters (HCCPARAMS) register is a 4 B register, and
the bit allocation is given in
Table 90.
Address: Value read from func2 of address 10h + 08h
Table 91.
Address: Value read from func2 of address 10h + 08h
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 8
7 to 4
3 and 2
1
0
Symbol
reserved
IST[3:0]
reserved
PFLF
64AC
HCCPARAMS - Host Controller Capability Parameters register bit allocation
HCCPARAMS - Host Controller Capability Parameters register bit description
31
23
15
R
R
R
R
0
0
0
7
0
Description
-
Isochronous Scheduling Threshold: Default = implementation dependent.
This field indicates—relative to the current position of the executing Host
Controller—where software can reliably update the isochronous schedule.
When IST[3] is logic 0, the value of the least significant three bits indicates
the number of micro frames a Host Controller can hold a set of isochronous
data structures—one or more—before flushing the state. When IST[3] is
logic 1, the host software assumes the Host Controller may cache an
isochronous data structure for an entire frame.
-
Programmable Frame List Flag: Default = implementation dependent. If
this bit is cleared, the system software must use a frame list length of
1024 elements with the Host Controller. The USBCMD register FLS[1:0]
(bit 3 and bit 2) is read-only and should be cleared. If PFLF is set, the system
software can specify and use a smaller frame list and configure the host
through the FLS bit. The frame list must always be aligned on a 4 kB page
boundary to ensure that the frame list is always physically contiguous.
64-bit Addressing Capability: This field contains the addressing range
capability.
0 — Data structures using 32-bit address memory pointers
1 — Data structures using 64-bit address memory pointers
Rev. 01 — 7 February 2007
30
22
14
R
R
R
R
0
0
0
6
0
IST[3:0]
Table
29
21
13
90.
R
R
R
R
0
0
0
5
0
Hi-Speed Universal Serial Bus PCI Host Controller
28
20
12
R
R
R
R
0
0
0
4
1
reserved
reserved
reserved
27
19
11
R
R
R
R
0
0
0
3
0
reserved
26
18
10
R
R
R
R
2
0
0
0
0
SAF1562
© NXP B.V. 2007. All rights reserved.
PFLF
25
17
R
R
R
R
0
0
9
0
1
1
64AC
63 of 97
24
16
R
R
R
R
0
0
8
0
0
0