SAF1562HL NXP [NXP Semiconductors], SAF1562HL Datasheet - Page 42

• Manufacturer Part Number: SAF1562HL
• Description: Hi-Speed Universal Serial Bus PCI Host Controller
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
SAF1562_1
Product data sheet
[1]
Table 53.
Address: Value read from func0 or func1 of address 10h + 14h
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31
30
29 to 7
6
5
4
3
2
1
0
The reserved bits should always be written with the reset value.
reserved
Symbol
MIE
OC
reserved
RHSC
FNO
UE
RD
SF
WDH
SO
HcInterruptDisable - Host Controller Interrupt Disable register bit description
R/W
R/W
15
0
7
0
[1]
Rev. 01 — 7 February 2007
Description
Master Interrupt Enable:
0 — Ignore
1 — Disables interrupt generation because of events specified in other
bits of this register
This field is set after a hardware or software reset. Interrupts are
disabled.
Ownership Change:
0 — Ignore
1 — Disables interrupt generation because of Ownership Change
-
Root Hub Status Change:
0 — Ignore
1 — Disables interrupt generation because of Root Hub Status Change
Frame Number Overflow:
0 — Ignore
1 — Disables interrupt generation because of Frame Number Overflow
Unrecoverable Error:
0 — Ignore
1 — Disables interrupt generation because of Unrecoverable Error
Resume Detect:
0 — Ignore
1 — Disables interrupt generation because of Resume Detect
Start-of-Frame:
0 — Ignore
1 — Disables interrupt generation because of Start-of-Frame
HcDoneHead Writeback:
0 — Ignore
1 — Disables interrupt generation because of HcDoneHead Writeback
Scheduling Overrun:
0 — Ignore
1 — Disables interrupt generation because of Scheduling Overrun
RHSC
R/W
R/W
14
0
6
0
FNO
R/W
R/W
13
0
5
0
Hi-Speed Universal Serial Bus PCI Host Controller
R/W
R/W
UE
12
reserved
0
4
0
[1]
R/W
R/W
RD
11
0
3
0
R/W
R/W
SF
10
0
2
0
SAF1562
© NXP B.V. 2007. All rights reserved.
WDH
R/W
R/W
9
0
1
0
R/W
R/W
42 of 97
SO
8
0
0
0