SAF1562HL NXP [NXP Semiconductors], SAF1562HL Datasheet - Page 18

• Manufacturer Part Number: SAF1562HL
• Description: Hi-Speed Universal Serial Bus PCI Host Controller
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
SAF1562_1
Product data sheet
8.2.1.7 Cache Line Size register
The Class Code register is divided into three byte-size fields. The upper byte is a base
class code that broadly classifies the type of function the device performs. The middle
byte is a sub-class code that identifies more specifically the function of the device. The
lower byte identifies a specific register-level programming interface, if any, so that
device-independent software can interact with the device.
Table 11.
[1]
Table 12.
The Cache Line Size register is a read and write single-byte register that specifies the
system Cache Line size in units of double word. This register must be implemented by
master devices that can generate the Memory Write and Invalidate command. The value
in this register is also used by master devices to determine whether to use Read, Read
Line or Read Multiple command to access the memory.
Slave devices that want to allow memory bursting using a Cache Line-wrap addressing
mode must implement this register to know when a burst sequence wraps to the
beginning of the Cache Line.
This field must be initialized to logic 0 on activation of RST#.
description of the Cache Line Size register.
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
23 to 16
15 to 8
7 to 0
Bit
Symbol
Reset
Access
X is 1h for OHCI1 and OHCI2; X is 2h for EHCI.
Class Code register (address 09h) bit allocation
Class Code register (address 09h) bit description
Symbol
BCC[7:0]
SCC[7:0]
RLPI[7:0]
15
23
R
R
7
R
Rev. 01 — 7 February 2007
14
22
R
R
R
6
Description
Base Class Code: 0Ch is the base class code assigned to this byte. It
implies a serial bus controller.
Sub-Class Code: 03h is the sub-class code assigned to this byte. It
implies the USB Host Controller.
Register-Level Programming Interface: 10h is the programming
interface code assigned to OHCI, which is USB 1.1 specification
compliant. 20h is the programming interface code assigned to EHCI,
which is USB 2.0 specification compliant.
13
21
R
R
5
R
Hi-Speed Universal Serial Bus PCI Host Controller
12
20
R
R
R
4
RLPI[7:0]
SCC[7:0]
BCC[7:0]
X0h
0Ch
03h
[1]
11
19
R
R
3
R
Table 13
10
18
R
R
2
R
shows the bit
SAF1562
© NXP B.V. 2007. All rights reserved.
17
R
R
R
9
1
18 of 97
16
R
R
8
0
R