SAF1562HL NXP [NXP Semiconductors], SAF1562HL Datasheet - Page 71

• Manufacturer Part Number: SAF1562HL
• Description: Hi-Speed Universal Serial Bus PCI Host Controller
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
SAF1562_1
Product data sheet
11.3.5 PERIODICLISTBASE register
Table 99.
Address: Value read from func2 of address 10h + 2Ch
The Periodic Frame List Base Address (PERIODLISTBASE) register contains the
beginning address of the periodic frame list in the system memory. If the Host Controller is
in 64-bit mode—as indicated by logic 1 in 64AC (bit 0 of the HCCSPARAMS register)—the
most significant 32 bits of every control data structure address comes from the
CTRLDSSEGMENT register. The system software loads this register before starting the
schedule execution by the Host Controller. The memory structure referenced by this
physical memory pointer is assumed as 4 kB aligned. The contents of this register are
combined with the FRINDEX register to enable the Host Controller to step through the
periodic frame list in sequence.
The bit allocation is given in
Table 100. PERIODICLISTBASE - Periodic Frame List Base Address register bit allocation
Address: Value read from func2 of address 10h + 34h
Bit
31 to 14
13 to 0
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Symbol
reserved
FRINDEX
[13:0]
FRINDEX - Frame Index register bit description
R/W
R/W
R/W
31
23
15
0
0
0
Description
-
Frame Index: Bits in this register are used for the frame number in the SOF
packet and as the index into the frame list. The value in this register
increments at the end of each time frame. For example, micro frame. The
bits used for the frame number in the SOF token are taken from bits 13 to 3
of this register. Bits N to 3 are used for the frame list current index. This
means that each location of the frame list is accessed eight times—frames
or micro frames—before moving to the next index.
The following illustrates values of N based on the value of FLS[1:0]
(bit 3 and bit 2 in the USBCMD register).
Rev. 01 — 7 February 2007
R/W
R/W
R/W
30
22
14
0
0
0
BA[3:0]
Table
FLS[1:0]
R/W
R/W
R/W
00b
01b
10b
11b
29
21
13
0
0
0
100.
Hi-Speed Universal Serial Bus PCI Host Controller
R/W
R/W
R/W
28
20
12
0
0
0
BA[19:12]
BA[11:4]
Number elements
R/W
R/W
R/W
27
19
11
0
0
0
reserved
1024
512
256
R/W
R/W
R/W
26
18
10
0
0
0
reserved
SAF1562
© NXP B.V. 2007. All rights reserved.
R/W
R/W
R/W
[1]
N
12
11
10
-
25
17
0
0
9
0
R/W
R/W
R/W
71 of 97
24
16
0
0
8
0