SAF1562HL NXP [NXP Semiconductors], SAF1562HL Datasheet - Page 68

• Manufacturer Part Number: SAF1562HL
• Description: Hi-Speed Universal Serial Bus PCI Host Controller
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
SAF1562_1
Product data sheet
11.3.3 USBINTR register
Table 95.
Address: Value read from func2 of address 10h + 24h
The USB Interrupt Enable (USBINTR) register enables and disables reporting of the
corresponding interrupt to the software. When a bit is set and the corresponding interrupt
is active, an interrupt is generated to the host. Interrupt sources that are disabled in this
register still appear in USBSTS to allow the software to poll for events. The USBSTS
register bit allocation is given in
Bit
11 to 6
5
4
3
2
1
0
USBSTS - USB Status register bit description
Symbol
reserved
IAA
HSE
FLR
PCD
USB
ERRINT
USBINT
Rev. 01 — 7 February 2007
Description
-
Interrupt on Asynchronous Advance: Default = logic 0. The system
software can force the Host Controller to issue an interrupt the next time
the Host Controller advances the asynchronous schedule by writing
logic 1 to IAAD (bit 6) in the USBCMD register. This status bit indicates
the assertion of that interrupt source.
Host System Error: The Host Controller sets this bit when a serious
error occurs during a host system access, involving the Host Controller
module. In a PCI system, conditions that set this bit include PCI parity
error, PCI master abort and PCI target abort. When this error occurs,
the Host Controller clears RS (bit 0 in the USBCMD register) to prevent
further execution of the scheduled TDs.
Frame List Rollover: The Host Controller sets this bit to logic 1 when
the frame list index rolls over from its maximum value to zero. The exact
value at which the rollover occurs depends on the frame list size. For
example, if the frame list size—as programmed in FLS (bit 3 and bit 2)
of the USBCMD register—is 1024, the Frame Index register rolls over
every time bit 13 of the FRINDEX register toggles. Similarly, if the size is
512, the Host Controller sets this bit to logic 1 every time bit 12 of the
FRINDEX register toggles.
Port Change Detect: The Host Controller sets this bit to logic 1 when
any port— where PO (bit 13 of PORTSC) is cleared—changes to
logic 1, or FPR (bit 6 of PORTSC) changes to logic 1 as a result of a
J-to-K transition detected on a suspended port. This bit is allowed to be
maintained in the auxiliary power well. Alternatively, it is also acceptable
that—on a D3-to-D0 transition of the EHCI Host Controller device—this
bit is loaded with the logical OR of all the PORTSC change bits,
including force port resume, overcurrent change, enable or disable
change, and connect status change.
USB Error Interrupt: The Host Controller sets this bit when an error
condition occurs because of completing a USB transaction. For
example, error counter underflow. If the Transfer Descriptor (TD) on
which the error interrupt occurred also had its IOC bit set, both this bit
and the USBINT bit are set. For details, refer to the Enhanced Host
Controller Interface Specification for Universal Serial Bus Rev. 1.0 .
USB Interrupt: The Host Controller sets this bit on completing a USB
transaction, which results in the retirement of a TD that had its IOC bit
set. The Host Controller also sets this bit when a short packet is
detected, that is, the actual number of bytes received was less than the
expected number of bytes. For details, refer to the Enhanced Host
Controller Interface Specification for Universal Serial Bus Rev. 1.0 .
Table
Hi-Speed Universal Serial Bus PCI Host Controller
96.
…continued
SAF1562
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