SAF1562HL NXP [NXP Semiconductors], SAF1562HL Datasheet - Page 25

• Manufacturer Part Number: SAF1562HL
• Description: Hi-Speed Universal Serial Bus PCI Host Controller
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
SAF1562_1
Product data sheet
8.2.3.3 PMC register
Table 32.
Address: Value read from address 34h + 1h
Legend: * reset value
The Power Management Capabilities (PMC) register is a 2 B register, and the bit
allocation is given in
function related to power management.
Table 33.
Address: Value read from address 34h + 2h
[1]
Table 34.
Address: Value read from address 34h + 2h
Bit
7 to 0 NEXT_ITEM_
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
15 to 11 PME_S
10
9
X = logic 0 for OHCI1 and OHCI2; X = logic 1 for EHCI.
Symbol
PTR[7:0]
Symbol
[4:0]
D2_S
D1_S
Next_Item_Ptr - Next Item Pointer register bit description
PMC - Power Management Capabilities register bit allocation
PMC - Power Management Capabilities register bit description
15
R
R
1
7
1
AUX_C[1:0]
Description
PME_Support: These bits indicate the power states in which the function
may assert PME#. Logic 0 for any bit indicates that the function is not
capable of asserting the PME# signal while in that power state.
PME_S[0] — PME# can be asserted from D0
PME_S[1] — PME# can be asserted from D1
PME_S[2] — PME# can be asserted from D2
PME_S[3] — PME# can be asserted from D3
PME_S[4] — PME# can be asserted from D3
D2_Support: If this bit is logic 1, this function supports the D2 Power
Management State. Functions that do not support D2 must always return
logic 0 for this bit.
D1_Support: If this bit is logic 1, this function supports the D1 Power
Management State. Functions that do not support D1 must always return
logic 0 for this bit.
Table
Rev. 01 — 7 February 2007
Access Value
R
14
R
R
1
6
0
33. This register provides information on the capabilities of the
PME_S[4:0]
00h*
DSI
X
13
R
R
5
0
[1]
Hi-Speed Universal Serial Bus PCI Host Controller
Description
Next Item Pointer: This field provides an offset into
the function’s PCI configuration space, pointing to the
location of the next item in the function’s capability list.
If there are no additional items in the capabilities list,
this register is set to 00h.
reserved
12
R
R
1
4
0
PMI
X
11
R
R
3
0
[1]
hot
cold
D2_S
X
10
R
R
2
0
[1]
VER[2:0]
SAF1562
© NXP B.V. 2007. All rights reserved.
D1_S
R
R
9
1
1
1
AUX_C
25 of 97
R
R
8
0
0
0