SAF1562HL NXP [NXP Semiconductors], SAF1562HL Datasheet - Page 60

• Manufacturer Part Number: SAF1562HL
• Description: Hi-Speed Universal Serial Bus PCI Host Controller
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
SAF1562_1
Product data sheet
11.2.1 CAPLENGTH/HCIVERSION register
11.2 EHCI controller capability registers
Table 85.
Address: Value read from func0 or func1 of address 10h + 54h
Other than the OHCI Host Controller, there are some registers in EHCI that define the
capability of EHCI. The address range of these registers is located before the operational
registers.
The bit allocation of this 4 B register is given in
Bit
2
1
0
Symbol
PSS
PES
CCS
HcRhPortStatus[4:1] - Host Controller Root Hub Port Status[4:1] register bit
description
Description
On read—Port Suspend Status: This bit indicates whether the port is
suspended or is in the resume sequence. It is set by a Set Suspend State
write and cleared when PSSC (Port Suspend Status Change) is set at the
end of the resume interval. This bit is not set if CCS (Current Connect
Status) is cleared. This bit is also cleared when PRSC is set at the end of
the port reset or when the Host Controller is placed in the USBRESUME
state. If an upstream resume is in progress, it will propagate to the Host
Controller.
0 — Port is not suspended
1 — Port is suspended
On write—Set Port Suspend: The HCD can set the PSS (Port Suspend
Status) bit by writing logic 1 to this bit. Writing logic 0 has no effect. If CCS
is cleared, this write does not set PSS; instead it sets CSS. This informs the
driver that it attempted to suspend a disconnected port.
On read—Port Enable Status: This bit indicates whether the port is
enabled or disabled. The Root Hub may clear this bit when an overcurrent
condition, disconnect event, switched-off power or operational bus error is
detected. This change also causes Port Enabled Status Change to be set.
The HCD can set this bit by writing Set Port Enable and clear it by writing
Clear Port Enable. This bit cannot be set when CCS (Current Connect
Status) is cleared. This bit is also set on completing a port reset when
Reset Status Change is set or on completing a port suspend when
Suspend Status Change is set.
0 — Port is disabled
1 — Port is enabled
On write—Set Port Enable: The HCD can set PES (Port Enable Status) by
writing logic 1. Writing logic 0 has no effect. If CCS is cleared, this write
does not set PES, but instead sets CSC (Connect Status Change). This
informs the driver that it attempted to enable a disconnected port.
On read—Current Connect Status: This bit reflects the current state of the
downstream port.
0 — No device connected
1 — Device connected
On write—Clear Port Enable: The HCD can write logic 1 to this bit to clear
the PES (Port Enable Status) bit. Writing logic 0 has no effect. The CCS bit
is not affected by any write.
Remark: This bit always reads logic 1 when the attached device is
nonremovable (Device Removable [NDP]).
Rev. 01 — 7 February 2007
…continued
Hi-Speed Universal Serial Bus PCI Host Controller
Table
86.
SAF1562
© NXP B.V. 2007. All rights reserved.
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