SAF1562HL NXP [NXP Semiconductors], SAF1562HL Datasheet - Page 56

• Manufacturer Part Number: SAF1562HL
• Description: Hi-Speed Universal Serial Bus PCI Host Controller
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
SAF1562_1
Product data sheet
[1]
Table 83.
Address: Value read from func0 or func1 of address 10h + 50h
Bit
Symbol
Reset
Access
Bit
31
30 to 18 reserved
17
16
15
14 to 2
1
0
The reserved bits should always be written with the reset value.
Symbol
CRWE
CCIC
LPSC
DRWE
reserved
OCI
LPS
HcRhStatus - Host Controller Root Hub Status register bit description
R/W
7
0
Description
On write—Clear Remote Wakeup Enable:
0 — No effect
1 — Clears DRWE (Device Remote Wakeup Enable)
-
Over Current Indicator Change: This bit is set by hardware when a
change has occurred to the OCI bit of this register.
0 — No effect
1 — The HCD clears this bit
On read—Local Power Status Change: The Root Hub does not support
the local power status feature. Therefore, this bit is always logic 0.
On write—Set Global Power: In global power mode
(Power Switching Mode = logic 0), logic 1 is written to this bit to turn on
power to all ports (clear Port Power Status). In per-port power mode, it sets
Port Power Status only on ports whose Port Power Control Mask bit is not
set. Writing logic 0 has no effect.
On read—Device Remote Wakeup Enable: This bit enables bit Connect
Status Change (CSC) as a resume event, causing a state transition from
USBSUSPEND to USBRESUME and setting the Resume Detected
interrupt.
0 — CSC is not a remote wake-up event
1 — CSC is a remote wake-up event
On write—Set Remote Wakeup Enable: Writing logic 1 sets DRWE
(Device Remote Wakeup Enable). Writing logic 0 has no effect.
-
Over Current Indicator: This bit reports overcurrent conditions when
global reporting is implemented. When set, an overcurrent condition exists.
When cleared, all power operations are normal. If the per-port overcurrent
protection is implemented, this bit is always logic 0.
On read—Local Power Status: The Root Hub does not support the local
power status feature. Therefore, this bit is always read as logic 0.
On write—Clear Global Power: In global power mode
(Power Switching Mode = logic 0), logic 1 is written to this bit to turn off
power to all ports (clear Port Power Status). In per-port power mode, it
clears Port Power Status only on ports whose Port Power Control Mask bit
is not set. Writing logic 0 has no effect.
Rev. 01 — 7 February 2007
R/W
6
0
R/W
5
0
reserved
Hi-Speed Universal Serial Bus PCI Host Controller
R/W
[1]
4
0
R/W
3
0
R/W
2
0
SAF1562
© NXP B.V. 2007. All rights reserved.
OCI
R
1
0
LPS
RW
56 of 97
0
0