SAF1562HL NXP [NXP Semiconductors], SAF1562HL Datasheet - Page 37

• Manufacturer Part Number: SAF1562HL
• Description: Hi-Speed Universal Serial Bus PCI Host Controller
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
SAF1562_1
Product data sheet
Table 46.
Address: Value read from func0 or func1 of address 10h + 08h
[1]
Table 47.
Address: Value read from func0 or func1 of address 10h + 08h
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 18
17 and 16
15 to 4
3
The reserved bits should always be written with the reset value.
HcCommandStatus - Host Controller Command Status register bit allocation
HcCommandStatus - Host Controller Command Status register bit description
Symbol
reserved
SOC[1:0]
reserved
OCR
R/W
R/W
R/W
R/W
31
23
15
0
0
0
7
0
Rev. 01 — 7 February 2007
R/W
R/W
R/W
R/W
Description
-
Scheduling Overrun Count: The bit is incremented on each scheduling
overrun error. It is initialized to 00b and wraps around at 11b. It must be
incremented when a scheduling overrun is detected, even if SO (bit 0 in
HcInterruptStatus) is already set. This is used by the HCD to monitor any
persistent scheduling problems.
-
Ownership Change Request: This bit is set by an OS HCD to request a
change of control of the Host Controller. When set, the Host Controller
must set OC (bit 30 in HcInterruptStatus). After the changeover, this bit is
cleared and remains so until the next request from the OS HCD.
30
22
14
0
0
0
6
0
reserved
R/W
R/W
R/W
R/W
[1]
29
21
13
0
0
0
5
0
reserved
Hi-Speed Universal Serial Bus PCI Host Controller
R/W
R/W
R/W
R/W
[1]
28
20
12
0
0
0
4
0
reserved
reserved
OCR
R/W
R/W
R/W
R/W
[1]
[1]
27
19
11
0
0
0
3
0
R/W
R/W
R/W
R/W
BLF
26
18
10
2
0
0
0
0
SAF1562
© NXP B.V. 2007. All rights reserved.
R/W
R/W
R/W
CLF
R/W
25
17
0
0
9
0
1
0
SOC[1:0]
HCR
R/W
R/W
R/W
R/W
37 of 97
24
16
0
0
8
0
0
0