SAF1562HL NXP [NXP Semiconductors], SAF1562HL Datasheet - Page 10

• Manufacturer Part Number: SAF1562HL
• Description: Hi-Speed Universal Serial Bus PCI Host Controller
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
SAF1562_1
Product data sheet
7.4 Hi-Speed USB analog transceivers
7.5 Power management
7.6 Phase-Locked Loop (PLL)
7.7 Power-On Reset (POR)
7.8 Power supply
The EHCI is responsible for the port-routing switching mechanism. Two register bits are
used for ownership switching. During power-on and system reset, the default ownership of
all downstream ports is the OHCI. The Enhanced Host Controller Driver (EHCD) controls
the ownership during normal functionality.
The Hi-Speed USB analog transceivers directly interface to the USB cables through
integrated termination resistors. These transceivers can transmit and receive serial data
at all data rates: high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed
(1.5 Mbit/s).
The SAF1562HL provides an advanced power management capability interface that is
compliant with PCI Bus Power Management Interface Specification Rev. 1.1 . Power is
controlled and managed by the interaction between drivers and PCI registers.
For a detailed description on power management, see
A 12 MHz-to-30 MHz and 48 MHz clock multiplier PLL is integrated on-chip. This allows
the use of a low-cost 12 MHz crystal, which also minimizes EMI. No external components
are required for the PLL to operate.
Figure 3
start with 1. At t1, the detector passes through the trip level. Another delay will be added
before POR drops to 0 to ensure that the length of the generated detector pulse, POR, is
large enough to reset asynchronous flip-flops. If the dip is too short (t4 to t5 < 11 s),
POR will not react and will stay LOW.
Figure 4
Fig 3. Power-on reset
V
shows a possible curve of V
shows the SAF1562HL power supply connection.
POR(trip)
t0
is typically 1.2 V.
t1
Rev. 01 — 7 February 2007
Hi-Speed Universal Serial Bus PCI Host Controller
CC(I/O)
t2
with dips at t2 to t3 and t4 to t5. At t0, POR will
t3
Section
t4
t5
10.
004aaa664
SAF1562
© NXP B.V. 2007. All rights reserved.
V
V
POR
CC(I/O)
POR(trip)
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