SAF1562HL NXP [NXP Semiconductors], SAF1562HL Datasheet - Page 21

• Manufacturer Part Number: SAF1562HL
• Description: Hi-Speed Universal Serial Bus PCI Host Controller
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
SAF1562_1
Product data sheet
8.2.1.14 Interrupt Line register
8.2.1.15 Interrupt Pin register
8.2.1.16 Min_Gnt and Max_Lat registers
This is a 1 B register used to communicate interrupt line routing information. This register
must be implemented by any device or device function that uses an interrupt pin. The
interrupt allocation is done by the BIOS. The POST software needs to write the routing
information to this register because it initializes and configures the system.
The value in this register specifies which input of the system interrupt controller(s) the
interrupt pin of the device is connected. This value is used by device drivers and operating
systems to determine priority and vector information. Values in this register are system
architecture specific. The bit description of the register is given in
Table 21.
Legend: * reset value
This 1 B register is use to specify which interrupt pin the device or device function uses.
A value of 1h corresponds to INTA#, 2h corresponds to INTB#, 3h corresponds to INTC#,
and 4h corresponds to INTD#. Devices or functions that do not use interrupt pin must set
this register to logic 0. The bit description is given in
Table 22.
Legend: * reset value
The Minimum Grant (Min_Gnt) and Maximum Latency (Max_Lat) registers are used to
specify the desired settings of the device for latency timer values. For both registers, the
value specifies a period of time in units of 250 ns. Logic 0 indicates that the device has no
major requirements for setting latency timers.
The Min_Gnt register bit description is given in
Table 23.
Legend: * reset value
[1]
The Max_Lat register bit description is given in
Bit
7 to 0 IL[7:0]
Bit
7 to 0 IP[7:0]
Bit
7 to 0 MIN_GNT
X is 1h for OHCI1 and OHCI2; X is 2h for EHCI.
Symbol
Symbol
Symbol
[7:0]
IL - Interrupt Line register (address 3Ch) bit description
IP - Interrupt Pin register (address 3Dh) bit description
Min_Gnt - Minimum Grant register (address 3Eh) bit description
Access
R/W
Access
R
Access
R
Rev. 01 — 7 February 2007
Value
0Xh*
Value
00h*
Value
01h*
[1]
Hi-Speed Universal Serial Bus PCI Host Controller
Description
Min_Gnt: It is used to specify how long a burst period
the device needs, assuming a clock rate of 33 MHz.
Description
Interrupt Line: Indicates which IRQ is used to report
interrupt from the SAF1562HL.
Description
Interrupt Pin: INTA# is the default interrupt pin used
by the SAF1562HL.
Table
Table
Table
23.
24.
22.
Table
SAF1562
© NXP B.V. 2007. All rights reserved.
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